The excessive depletion of groundwater resources and significant climate change have exerted immense pressure on global groundwater reserves. Owing to the rising global demand for drinking water, as well as its use in agriculture and industry, there is an increasing need to evaluate the capacity and effectiveness of underground water reservoirs (aquifers). Recently, GIS has gained significant attention for groundwater exploration because of its ability to provide rapid and comprehensive information about resources for further development. This study aims to assess and map the groundwater potential of a large basin located in the southern region of Saudi Arabia. Techniques such as GIS and AHP were employed in this study. To perform the delineation for the groundwater potential zones (GWPZ), seven thematic layers were prepared and analyzed. These layers include geology, slope, land use, lineament densities, soil characteristics, drainage density, and rainfall. These variables were carefully considered and examined to identify and categorize areas based on their respective groundwater potentials. The assigned weights to each class in the thematic maps were determined using the well-known analytic hierarchy process (AHP) method. This methodology considered the characteristics of each class and their capacity to influence water potential. The results’ precision was verified by cross-referencing it with existing information about the area’s potential for groundwater. The resulting GWPZ map was classified into the following five categories: very low, low, moderate, high, and very high. The study revealed that approximately 42.56% of the basin is classified as having a high GWPZ. The low and moderate potential zones cover 36.12% and 19.55% of the area, respectively. Very low and very high potential zones were found only in a limited number of areas within the basin. This study holds global importance as it addresses the pressing challenge of depleting groundwater resources. With rising demands for drinking water, agriculture, and industry worldwide, the effective evaluation and management of underground water reservoirs are crucial. By utilizing GIS and AHP techniques, this study provides a valuable assessment and the mapping of groundwater potential in a large basin in southern Saudi Arabia. Its findings and methodology can serve as a model for other regions, supporting sustainable water resource management globally.

A novel platform for launching and using Field Programmable Gate Arrays (FPFA) custom computing machines (CCMs) in clouds and data centers is proposed. Based on a developed FPGA virtualization scheme, it allows users to create independent computing services on network-attached standalone FPGAs. The interface of the virtual FPGA (vFPGA)-based CCM is automatically generated by a virtualization layer and based on the user’s specifications. An FPGA hypervisor have been developed that can be easily integrated with any cloud management tool. It allows the users to launch/use/tear down vFPGA-based CCMs on a similar manner to conventional virtual machines. A complete prototype of the proposed platform has been realized and tested with a streamed image processing application. Its performance was 3~4x and ~1.4–2.4x times better than a SW implementation on a VM and a powerful server, respectively. Compared with other platforms for FPGA attachment to a cloud or datacenter, the proposed platform has a relatively low overhead in terms of FPGA resources while providing highest level of abstraction and virtualization.

Simulation is the main tool for computer architects and parallel application developers for developing new architectures and parallel algorithms on many-core machines. Simulating a many-core architecture represent a challenge to software simulators even with parallelization of these SW on multi-cores. Field Programmable Gate Arrays offer an excellent implementation platform due to inherent parallelism. Existing FPGA-based simulators however, are mostly execution-driven which consumes too many FPGA resources. Hence, they still trade-off accuracy with simulation speed as SW simulators do. In this work, an application-level trace-driven FPGA-based many-core simulator is presented. A parameterized Verilog template was developed that can generate any number of simulator tiles. The input trace has an architecturally agnostic format that is directly interpreted by the FPGA-based timing model to re-construct the execution events of the original application with accurate timing. This allows fitting a large number of simulation tiles on a single FPGA without sacrificing simulation speed or accuracy. Experimental results show that the simulator's average accuracy is ~14 percent with simulation speeds ranging from 100's of MIPs to over 2,200 MIPS for a 16-core target architecture. Hence, with accuracy similar to SW simulators, its speed is higher than all other FPGA-based simulators.

A novel method for the high-speed test and characterization of digital integrated circuit prototypes has been developed. It utilizes a specially developed off-chip processor and supporting circuitry that is to be included on the prototype chip to facilitate the test and characterization process. The processor administers the user-defined test, receives and stores the test results. The test procedure and data is downloaded to the processor's memory through a standard interface. The supporting circuitry receives the test data serially from the processor, apply it to the selected circuit within the IC, collect and reformat the test results and send it to the processor. It also includes a high-frequency configurable clock generator to be used for performance characterization of the prototyped circuits. This allows the interface between the processor and the prototype chip to be fixed with any circuits being prototyped and tested. This unique hybrid solution, enables testing at full speed with minimal cost compared to the current method of using highspeed test equipments. The proposed method was validated with a complete prototype using FPGAs. A complete layout of the onchip support circuitry with 4 circuit prototypes had a total area of ~0.01 mm² using Lfoundry's 150 nm technology.