In this study, we present a polynomial basis multiplication architecture based on cellular systolic hardware architecture for Montgomery multiplication over Galois fields by adopting a qualified Montgomery factor which is highly suitable for the design on our structures. At first, we propose a parallel computation algorithm which operates two independent computations. The algorithm is efficiently designed by reordering the sequence of the terms on the polynomial. Second, we construct an ideal architecture which is composed of two independent parts. Our architecture is possible to compute two parts simultaneously. Each part is composed of same cell structures so that it is easy to be generalized and scalable. Finally, we obtain a time-saved architecture in a large degree with high scalability.

In this letter, we propose a parallel-in parallel-out systolic array for concurrently computing multiplication and squaring over GF(2m). For m ≥ 400, the proposed bit-parallel systolic array can save about 50% time complexity as compared to the corresponding existing structure. The proposed array can be used as a core circuit for various applications. Also our architecture is well suited to VLSI implementation as well.