This paper presents a survey of the different modern High-Level Synthesis (HLS) Design Space Exploration (DSE) techniques that have been proposed so far to automatically generate hardware accelerators of different trade-offs. HLS has multiple advantages compared to traditional RT-level based hardware design. One key advantage is that a variety of different micro-architectures of unique trade-offs can be obtained from the same untimed behavioral description by setting different synthesis options. Out of all the possible micro-architectures, the ones that the designers are most interested in are the Pareto-optimal ones. The main problem is that the search space grows superlinearly with the number of synthesis options and hence heuristics have been proposed to search the space efficiently. This paper summarizes the main techniques proposed and addresses critical issues still not resolved as well identifies new opportunities in this field. It also serves as a guide for anyone wanting to create their own HLS DSE and introduces an open source graphical user interface (GUI) framework to facilitate this.

High-level synthesis (HLS) is being increasingly used for commercial VLSI designs. This has led to the proliferation of many HLS tools. In order to evaluate their performance and functionalities, a standard benchmark suite in a common language supported by all of them is required. This letter presents a benchmark suite, which complies with the latest Synthesizable SystemC standard, called S2CBench. The benchmarks have been carefully chosen to not only include applications of different sizes and from various domains typically used in HLS (e.g., encryption, image and DSP application), but also to test specific optimization techniques in each of them. This allows an easy comparison of not only quality of results (QoR) of the different HLS tools under review, but also to test their completeness.

A machine learning-based predictive model design space exploration (DSE) method for high-level synthesis (HLS) is presented. The method creates a predictive model for a training set until a given error threshold is reached and then continues with the exploration using the predictive model avoiding time-consuming synthesis and simulations of new configurations. Results show that the authors’ method is on average 1.92 times faster than a genetic-algorithm DSE method generating comparable results, whereas it achieves better results when constraining the DSE runtime. When compared with a previously developed simulated annealer (SA)-based method, the proposed method is on average 2.09 faster, although again achieving comparable results.

This paper presents a microarchitectural design space exploration tool called cwbexplorer based on an Adaptive Simulated Annealer Exploration Algorithm (ASA-ExpA) for behavioral descriptions written in untimed C or SystemC. Cwbexplorer automatically generates a series of designs given a set of constraints (area and latency) from an untimed high level language description. A commercial high level synthesis tool (Cy- berWorkBench) is used to synthesize each new architecture. The ASA-ExpA searches the design space based on the results of the previous synthesis, the global cost function and the given constraints. The global cost function weights are adaptively modified during the exploration to adjust the objective to minimize area or latency. Experimental results show that cwbexplorer successfully searches the design space fast and efficiently finding the smallest and fastest designs for most benchmarks, incurring in small penalties (5% in area and 8% in latency) for larger benchmarks while reducing the total runtime by an average of 66% compared to a brute force approach.

This paper presents a modified technique of simulated annealing, based on machine learning for effective multi-objective design space exploration in High Level Synthesis (HLS). In this work, we present a more efficient simulated annealing called Fast Simulated Annealer (FSA) which is based on a decision tree machine learning algorithm. Our proposed exploration method makes use of a standard simulated annealer to generate a training set, and uses this set to implement a decision tree. Based on the outcome of the decision tree, the algorithm fixes the synthesis directives (pragmas) which contribute to minimizing/maximizing one of the cost function objectives and continues the annealing procedure using the decision tree. Experimental results show that the average execution time of our proposed tree based simulated annealing algorithm is on average 36% faster than the standard annealer and can be up to 48% faster, while leading to similar results.

One of the biggest advantages of C-based very large scale integration design over traditional register transfer level is its ability to automatically generate architectures with different area versus performance characteristics without the need of modifying the original behavioral description. Different knobs can be explored to obtain the dominating tradeoff curve (Pareto-front). So far previous works have only focused on exploring one set of knobs or combining all of them together without considering the underlying implications of each of these knobs. This paper presents the first method that accelerates the design space exploration (DSE) by first classifying these knobs and exploring them sequentially, thus reducing the design space to be explored considerably. In particular: 1) local synthesis directives in the form of pragmas inserted directly at the source code and 2) functional units (FUs) number and type. Second, we propose a probabilistic method to further accelerate the DSE by computing the probability of each micro-architecture generated after the pragma exploration stage, to lead to new dominating designs and in turn exploring only those with the highest probabilities. One additional contribution is that the explorer for both knobs are implemented using novel heuristics. The pragma based explorer is based on ant colony optimization, while the FU explorer explores the number and type of FUs in order to further maximize the total amount of resource sharing that can be extracted. Experimental results show that our proposed method finds Pareto-fronts of similar quality than an exploration method optimized for quality of their results, while accelerating the DSE by an average of 12.2×.