This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (N_m). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to N_m = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10⁻³ missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the N_m ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.

This paper presents a passive Envelope Detector (ED) to be used for reception of OOK-modulated signals, such as in Wake-Up Receivers employed within Wireless Sensor Networks, widely used in the IoT. The main goal is implementing a temperature compensation mechanism in order to keep the passive ED input resistance roughly constant over temperature, making it a constant load for the preceding matching network and ultimately keeping the overall receiving chain sensitivity constant over temperature. The proposed ED was designed using STMicroelectronics 90 nm CMOS technology to receive 1 kbps OOK-modulated packets with a 433 MHz carrier frequency and a 0.6 V supply. The use of a block featuring a Proportional-to-Absolute Temperature (PTAT) current yields a 5 dB reduction in sensitivity temperature variation across the −40 °C to 120 °C range. Moreover, two different implementations were compared, one targeting minimal mismatch and the other one targeting minimal area. The minimal area version appears to be better in terms of estimated overall chain sensitivity at all temperatures despite a higher sensitivity spread.