Objectives. Following the completion of development stages due to transistor scaling (Dennard’s law) and an increased number of general-purpose processor cores (limited by Amdahl’s law), further improvements in the performance of computing systems naturally proceeds to the stage of developing specialized computing subsystems for performing specific tasks within a limited computational subclass. The development of such systems requires both the selection of the relevant high-demand tasks and the application of design techniques for achieving desired indicators within the developed specializations at very large scales of integration. The purpose of the present work is to develop a methodology for designing specialized computing systems based on the joint optimization of hardware and software in relation to a selected subclass of problems.Methods. The research is based on various methods for designing digital systems.Results. Approaches to the analysis of computational problems involving the construction of a computational graph abstracted from the computing platform, but limited by a set of architectural solutions, are considered. The proposed design methodology based on a register transfer level (RTL) representation synthesizer of a computing device is limited to individual computing architectures for which the relevant circuit is synthesized and optimized based on a high-level input description of the algorithm. Among computing node architectures, a synchronous pipeline and a processor core with a tree-like arithmetic-logical unit are considered. The efficiency of a computing system can be increased by balancing the pipeline based on estimates of the technological basis, and for the processor—based on optimizing the set of operations, which is performed based on the analysis of the abstract syntax tree graph with its optimal coverage by subgraphs corresponding to the structure of the arithmetic logic unit.Conclusions. The considered development approaches are suitable for accelerating the process of designing specialized computing systems with a massively parallel architecture based on pipeline or processor computing nodes.

Objectives. Developing the element base of field-programmable gate arrays (FPGA) may significantly affect the design of electronic devices due to the enhanced logical capacity of such chips and the general tendency towards increased subsystem integration. The system-on-a-chip (SoC) concept is aimed at combining receiving, processing, and exchange subsystems onto a single chip, as well as at implementing control, diagnostic, and other auxiliary subsystems. The study aimed at developing a method for soft processor applications, i.e., processors based on configurable logical resources, for implementing control functions in an FPGA-based SoC.Methods. A digital system design methodology was used.Results. For soft processors, a unified design route based on selecting architectural parameters qualitatively corresponding to control tasks was considered. In particular, such parameters as instruction set addressness, number of pipeline cycles, and arithmetic logic unit configuration are adjustable at the design stage to allow the optimization of the soft processor in the discrete parameter space. An approach to rapid prototyping of the assembler based on stack-oriented programming language with regular grammar was also considered. The control of digital signal processing hardware as part of an SoC is the promising application area for soft processors. An implementation is considered on the example of an SoC based on Xilinx Virtex-7 FPGA containing several processor cores developed using the proposed methodology.Conclusions. The considered approaches to soft processor design allow the rapid prototyping of the control processor core for operation as part of an FPGA-based SoC.

This article discusses the application of the method of approximation of experimental data by functional dependencies, which uses a probabilistic assessment of the deviation of the assumed dependence from experimental data. The application of this method involves the introduction of an independent parameter “scale of the error probability distribution function” and allows one to synthesize the deviation functions, forming spaces with a nonlinear metric, based on the existing assumptions about the sources of errors and noise. The existing method of regression analysis can be obtained from the considered method as a special case. The article examines examples of analysis of experimental data and shows the high resistance of the method to the appearance of single outliers in the sample under study. Since the introduction of an independent parameter increases the number of computations, for the practical application of the method in measuring and information systems, the architecture of a specialized computing device of the “system on a chip” class and practical approaches to its implementation based on programmable logic integrated circuits are considered.

The article deals with the design of specialized VLSI designed for the construction of high-performance computing systems. Common options for building such systems are general-purpose processors (CPUs), graphics accelerators (GPUs) that work in the mode of general-purpose computing acceleration, and FPGAs that are configured to implement a specific task or a narrow class of tasks. If there is a demanded class of tasks with specific requirements for computing resources, it is possible to develop a specialized VLSI that is more effective than CPU and GPU in terms of the use of crystal resources, and more productive than FPGA due to the use of hardware-implemented connections instead of programmable cells and switched trace lines. Taking into account modern trends in microelectronics and existing technological lag from leading global manufacturers, an important role is played by the choice of VLSI architecture as well as the use of architectural and circuit design solutions that reduce technical risks and provide solutions to urgent problems for Russian companies.

Objectives. The growing demand for higher computational performance and energy efficiency has motivated the increasing adoption of specialized heterogeneous computing systems incorporating hardware accelerators with massive parallelism. This paper aims to develop a methodology for the analysis and evaluation of hardware accelerator implementation strategies for large-scale parallel stream data processing which systematically captures all major directions of performance improvement. Methods . The study employs established techniques of digital system design and modeling. Results . A comparative evaluation method is introduced to assess the efficiency of heterogeneous computing architectures based on massively parallel hardware accelerators composed of independently programmable nodes. A computational acceleration ratio is defined which consolidates three key dimensions of accelerator improvement: algorithmic support and microarchitecture; design automation tools; and fabrication technologies (lithography). Furthermore, the study proposes an optimization-based methodology for the systematic analysis and evaluation of the alternatives for hardware accelerator implementation. Conclusions . The expressions derived herein for calculating the computational acceleration ratio and the aggregate throughput of hardware accelerators account for both multichannel and block-based massively parallel data stream processing. In contrast to conventional architectural exploration approaches, the evaluation method proposed herein enables hardware accelerator design alternatives to be assessed at the earliest stages of the design cycle. This incorporates variations in algorithmic versions and implementation strategies which influence hardware architecture optimization. The proposed methodology for analyzing and evaluating implementation options for hardware accelerators can be used to develop technical specifications for their manufacture, design them according to specified requirements, and justify configuration decisions. It can also support research and development assignments to achieve target characteristics for certain domain-specific tasks of massively parallel stream data processing and CAD capabilities.