The treatment of inoperable cancers in the therapy terminal in Lanzhou-China, which is located at the Institute of Modern Physics (IMP), permits to work on the actual front-end readout. The availability of detailed noise spectral density characteristics for the OPA amplifier helps to develop the noise error analysis for high-resolution. This work focused on the noise model of the detector-preamplifier, which presents the low noise circuit schematic of the Transimpedance (TIA). Considering the parasitical influences, we develop a new approach to detect the weak signals based on resonant frequency, 1/√L1 (C1+CGS). In addition, the system eliminates leakage current in the reset switch and reduces the charge injection occur from the switches in the Gated Integrator (GI) and the configuration switch is made especially with two transmission gates switches, in series, with a grounded MOS switch, attached to the node between the two transmission gates switches and the linearity almost good.

In this study, the objective is to realize a Gated Integrator (GI) circuit for silicon strip, Si(Li), CdZnTe and CsI detectors etc. With the development of radioactive ion beam physics, heavy-charged particles like carbon ions have been applied to the treatment of deep-seated inoperable tumors in the therapy terminal of the Heavy ion Research Facility in Lanzhou (HIRFL) located at the Institute of Modern Physics (IMP), Chinese Academy of Sciences (CAS). A high resolution current measurement circuit was developed to monitor the beam current at 1pA range. The circuit consisted of a low current high sensitivity I/V converter and gated integrator in an energy spectroscopy. A low offset voltage precision amplifier and new guarding and shielding techniques were used in the I/V converter circuit which allowed to measure low current. This paper will show a MOS switch configuration which is used to prevent leakage current and novel technique to compensate a charge injection in the reset switch.

This paper proposed a design of low-voltage Dynamic Comparator using 90 nm PTM CMOS technology for high-speed and Lower-power Analog to Digital Converter (ADC) applications. The double tail structure is employed as based for design new comparator with positive feedback due to best behavior in low-voltage that allows low delay time; decreases the offset voltage and power dissipation. Simulation results are presented with sampling frequency of 10GHZ. These results are also compared with earlier works interms of their delay time, power dissipation and offset voltage. The proposed comparator shows 5.7 mV offset which is small when compared to other dynamic comparators and preamplifier based comparators.