It is difficult to meet all the different material and economical requirements posed to a MEMS structural layer that can be integrated with the electronics on the same substrate using a single layer process. Therefore a multilayer process, which uses a combination of a CVD crystallization layer and a high-growth rate PECVD bulk layer was developed. High-quality films with excellent electrical and mechanical properties can be obtained at low temperature (#450°C) and high deposition rates (~100 nm/min). Fine-tuning of the stress gradient is accomplished by the use of a top stress compensation layer, whose optimal thickness was estimated from an evaluation of the stress gradient profile over thickness. These layers have been used for processing a 10 µm thick poly-SiGe gyroscope on top of a standard 0.35 µm CMOS process.

This paper reports on the experimental determination of the maximum post-process annealing temperature for standard 0.35 /spl mu/m CMOS wafers with aluminum based interconnections and tungsten plugs, without introducing significant modifications to their standard characteristics. The impact of increasing the post-processing temperature from 475/spl deg/C to 575/spl deg/C, for periods varying between 30 and 90 min, on both the front and back end is analyzed. 0.35 /spl mu/m CMOS technologies with different Al alloys, Al-1wt%Si-0.5wt%Cu (AlSiCu) or Al-0.5wt%Cu (AlCu), and different back end structures are considered. It is illustrated that the maximum annealing temperature is a function of the structure and composition of the interconnection layers and their maximum allowable resistance increase. It is also demonstrated that the transistor characteristics, the silicide quality and the leakage currents are as good as unaffected by annealing for 90 min at temperatures up to 525/spl deg/C.

Stresses were measured in 〈111〉‐textured Ag/Ni multilayered thin films from the substrate curvature and from lattice parameter measurements by x‐ray diffraction. The difference between the total multilayer film stress and the layer deposition stresses can be attributed to a tensile interface stress of −2.27±0.67 J/m². Interfacial phase formation is unlikely in this system as indicated by the exceptionally low mutual solubilities.

The biaxial modulus and coefficient of thermal expansion of ion-beam-sputtered amorphous Si and Ge thin films were determined from curvature changes induced by differential thermal expansion. Viscous flow was measured by stress relaxation and was found to be Newtonian. The viscosity increased linearly with time as a result of structural relaxation, and its isoconfigurational activation enthalpy was 1.8±0.3 and 2.6±1.3 eV for amorphous Si and Ge, respectively. An atomistic model, based on a chain reaction of broken bond rearrangements, is proposed to describe the observation.

In this work the etching of different Si-oxide, Si-nitride and metal layers in HF:H₂O 24.5:75.5, BHF:glycerol 2:1 and vapor HF is studied and compared. The vapor HF etching is done in a commercially available system for wafer cleaning, that was adapted according to custom specifications to enable stiction-free surface micro- machining. The etch rates as a function of etching method, time and temperature are determined. Moreover, the influence of internal and external parameters on the HF vapor etching process are analyzed before choosing the standard HF vapor etch technique used for comparing the etching behavior of the different films.