Internet of Things (IoT) has enabled battery-powered devices to transmit sensitive data, while presenting high power consumption and security issues. To address these challenges, adiabatic-based physical unclonable functions (PUFs) offer a promising solution for low-power and secure IoT device applications. In this study, we propose a novel low-power two-phase clocking adiabatic PUF. The proposed adiabatic PUF utilizes a trapezoidal power clock signal with a time-ramped voltage to achieve an improved energy efficiency and reliable start-up PUF behavior. Static CMOS logic is employed to produce stable challenge-response pairs (CRPs) in the adiabatic mode. The pull-down network is designed to control the PUF cell to charge and discharge its output nodes with a constant supply current during secure key generation. The body effect of PMOS transistors, ambient temperatures, and CMOS process variations are investigated to examine the uniqueness and reliability of the proposed work. The proposed adiabatic PUF is simulated using 0.18 µm CMOS process technology with a supply voltage of 1.8 V. The uniqueness and reliability of the proposed adiabatic PUF are 49.82% and 99.47%, respectively. In addition, it requires a start-up power of 0.47 µW and consumes an energy of 15.98 fJ/bit/cycle at the reference temperature of 27 °C.

Low-power and secure crypto-devices are in crucial demand for the current emerging technology of the Internet of Things (IoT). In nanometer CMOS technology, the static and dynamic power consumptions are in a very critical challenge. Therefore, the FinFETs is an alternative technology due to its superior attributes of non-leakage power, intra-die variability, low-voltage operation, and lower retention voltage of SRAMs. In this study, our previous work on CMOS two-phase clocking adiabatic physical unclonable function (TPCA-PUF) is evaluated in a FinFET device with a 4-bits PUF circuit complexity. The TPCA-PUF-based shorted-gate (SG) and independent-gate (IG) modes of FinFETs are investigated under various ambient temperatures, process variations, and ±20% of supply voltage variations. To validate the proposed TPCA-PUF circuit, the QUALPFU-based Fin-FETs are compared in terms of cyclical energy dissipation, the security metrics of the uniqueness, the reliability, and the bit-error-rate (BER). The proposed TPCA-PUF is simulated using 45 nm process technology with a supply voltage of 1 V. The uniqueness, reliability, and the BER of the proposed TPCA-PUF are 50.13%, 99.57%, and 0.43%, respectively. In addition, it requires a start-up power of 18.32 nW and consumes energy of 2.3 fJ/bit/cycle at the reference temperature of 27 °C.

The previously proposed charge‐sharing symmetric adiabatic logic (CSSAL) in an 8‐bit S‐box circuit is implemented in this paper using a multi‐stage positive polarity Reed–Muller representation with a composite field technique. The CSSAL and other conventional dual‐rail adiabatic logics are evaluated from the view point of the transitional power fluctuation and the peak current traces in the 8‐bit S‐box in order to compare their resistance against side‐channel attacks. A method to eliminate unwanted glitch current, the triple power clock supplies are applied to each inversion block; thus, the CSSAL S‐box circuit performs uniform peak current traces and it has significant power reduction, which is applicable for high security demand and low power devices, such as smart cards, radio frequency identity tags or wireless sensors. The results are obtained from the SPICE simulation with a 0.18‐μm 1.8‐V standard complementary metal–oxide semiconductor technology at an operating frequency band of 1.25 KHz–70 MHz.

Numerous works on advanced encryption standard (AES) S-box architecture have been done using composite field arithmetic in Galois field. However, to the best of our knowledge, less information is available on both a secure circuit and the low power consumption. In this work, we implement our previous proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit using multi-stage positive polarity Reed-Muller (PPRM) representation over composite field technique. The logic sharing method for frequently same logic function usage in the combination logic is applied. Consequently, the low-complexity, high resistive and the low-power consumption are achieved. The results in this paper are obtained from the SPICE simulation with 0.18-μm 1.8-V standard CMOS technology at operating frequency of 1.25-70 MHz. Base on the logic speed, security performance and low-power requirement, we deduce that our proposed logic is applicable for contactless smart cards, RFID tags, and wireless sensors.

This paper implements our proposed charge-sharing symmetric adiabatic logic (CSSAL) into the cellular multiplier used in finite field over GF(2^m) arithmetic using secure system for resistant against side-channel attacks. To validate our proposed logic, we have evaluated the current traces and energy dissipation of the individual secure adiabatic logics; proposed CSSAL, secure adiabatic logic, symmetric adiabatic logic, 2N-2N2P, and the conventional three-phase dual-rail pre-charged logic. Furthermore, the thoroughly investigation and comparative study on the logic's resistance and the energy efficiency in the multiplier over GF(2^m) have been conducted. Based on the obtained SPICE simulation results, we deduce that, the proposed typical logics is stronger against differential power analysis and more robust for differential electromagnetic analysis attacks, because it consumes constant low power and uniformly low peak current since ever in the literature.