Plasma etching processes at the 22 nm technology node and below will have to satisfy multiple stringent scaling requirements of microelectronics fabrication. To satisfy these requirements simultaneously, significant improvements in controlling key plasma parameters are essential. Pulsed plasmas exhibit considerable potential to meet the majority of the scaling challenges, while leveraging the broad expertise developed over the years in conventional continuous wave plasma processing. Comprehending the underlying physics and etching mechanisms in pulsed plasma operation is, however, a complex undertaking; hence the full potential of this strategy has not yet been realized. In this review paper, we first address the general potential of pulsed plasmas for plasma etching processes followed by the dynamics of pulsed plasmas in conventional high-density plasma reactors. The authors reviewed more than 30 years of academic research on pulsed plasmas for microelectronics processing, primarily for silicon and conductor etch applications, highlighting the potential benefits to date and challenges in extending the technology for mass-production. Schemes such as source pulsing, bias pulsing, synchronous pulsing, and others in conventional high-density plasma reactors used in the semiconductor industry have demonstrated greater flexibility in controlling critical plasma parameters such as ion and radical densities, ion energies, and electron temperature. Specifically, plasma pulsing allows for independent control of ion flux and neutral radicals flux to the wafer, which is key to eliminating several feature profile distortions at the nanometer scale. However, such flexibility might also introduce some difficulty in developing new etching processes based on pulsed plasmas. Therefore, the main characteristics of continuous wave plasmas and different pulsing schemes are compared to provide guidelines for implementing different schemes in advanced plasma etching processes based on results from a particularly challenging etch process in an industrial reactor.

This work focuses on the impact of oxidizing and reducing ash chemistries on the modifications of two porous SiOCH films with varied porosities (8% [low porosity (lp)-SiOCH] and 45% [high porosity (hp)-SiOCH]). The ash processes have been performed on SiOCH blanket wafers in either reactive ion etching (RIE) or downstream (DS) reactors. The modifications of the remaining film after plasma exposures have been investigated using different analysis techniques such as x-ray photoelectron spectroscopy, Fourier transform infrared spectroscopy (FTIR), x-ray reflectometry, mercury probe capacitance measurement $\left(C\text{‐}V\right)$ , and spectroscopic ellipsometry (SE). FTIR analyses show that the lp-SiOCH film is not significantly altered by any of the ash processes investigated ($\mathrm{DS}\text{‐}{\mathrm{H}}_2∕\mathrm{He}$ , $\mathrm{RIE}\text{‐}{\mathrm{O}}_2$ , and $\mathrm{RIE}\text{‐}{\mathrm{NH}}_3$ ), except by downstream oxidizing plasmas ($\mathrm{DS}\text{‐}{\mathrm{O}}_2$ or $\mathrm{DS}\text{‐}{\mathrm{N}}_2∕{\mathrm{O}}_2$ ) which induce some carbon depletion and moisture uptake, resulting in a slight increase of the $k$ value. The porosity amplifies the sensitivity of the material to plasma treatments. Indeed, hp-SiOCH is fully modified (moisture uptake and carbon depletion) under oxidizing downstream plasma exposures ($\mathrm{DS}\text{‐}{\mathrm{O}}_2$ and $\mathrm{DS}\text{‐}{\mathrm{N}}_2∕{\mathrm{O}}_2$ ), while it is partially altered with the formation of a denser and modified layer ($40–60\mathrm{nm}$ thick), which is carbon depleted, hydrophilic, and composed of $\mathrm{Si}{\mathrm{O}}_x{\mathrm{N}}_y{\mathrm{H}}_z$ with $\mathrm{RIE}\text{‐}\mathrm{N}{\mathrm{H}}_3$ and $\mathrm{DS}\text{‐}{\mathrm{N}}_2∕{\mathrm{H}}_2$ plasmas and $\mathrm{Si}{\mathrm{O}}_x{\mathrm{H}}_y$ with $\mathrm{RIE}\text{‐}{\mathrm{O}}_2$ plasma. In all the cases, the $k$ value increase is mainly attributed to the moisture uptake rather than methyl group consumption. hp-SiOCH material is not altered using reducing DS chemistries (${\mathrm{H}}_2∕\mathrm{He}$ and ${\mathrm{H}}_2∕\mathrm{Ar}$ ). The porous SiOCH film degradation is presented and discussed with respect to chemistry, plasma parameters, and plasma mode in terms of film modification mechanism.

Nanocomposite thin films containing indium nitride (InN) quantum dots (QDs) embedded in silicon (Si) matrix were prepared by the target-attachment sputtering method. X-ray photoelectron spectroscopy confirmed the presence of hexagonal InN phase in the samples and transmission electron microscopy revealed the single-crystalline InN QDs with the diameters ranging from 3.0 to 5.6 nm finely dispersed in Si matrix. The room-temperature photoluminescence (PL) analysis observed a sole emission with the peak at about 1155 nm (∼1.08 eV) for all samples in the measured wavelength range of 900 to 1600 nm. Such a PL emission was ascribed to the pinning effect of conduction band at the Fermi stabilization level of InN. Further, the PL intensity increased with the increase of incident laser power, implying the PL emission is correlated with the band-to-band transition in InN. The low-temperature PL analysis observed the dramatic increase of PL intensity and the shift of peak location toward the short wavelength side when the temperature was decreased. Meanwhile, the symmetry of emission peaks gradually improved owning to the suppression of the band tailing and thermal population effects.

In microelectronics technologies, patterning of sub-$100\mathrm{nm}$ width ridges capped with a titanium nitride mask can lead to undulations of the ridges detrimental to performances. This phenomenon is observed with highly compressive residual stress into the mask $(>2\mathrm{GPa})$ , with dielectrics with low elastic properties $(E<2\mathrm{Gpa})$ and with high dielectric ridge heights $(>230\mathrm{nm})$ . Experiments and simulations show that undulations can originate from buckling which allows the release of the strain energy initially stored in the mask. Simulations predict that the dielectric material undulations can become an issue for porous dielectrics integration in the next generations of integrated circuits (2016 and later).