This paper presents new architectures and implementations of original open-loop Class-BD audio amplifiers with balanced Common-Mode output. The output stage of each proposed amplifier includes the typical H-bridge with four MOSFETs and four additional MOSFET switches that balance and keep the Common-Mode output constant. The presented amplifiers employ the extended NBDD PWM or PSC PWM modulation scheme. When the output stage is built only on NMOSFET transistors, gate drivers require a floating power supply, using a self-boost charge pump with capacitive isolation of the control signal. The use of complementary MOSFETs in the output stage greatly simplifies gate control systems. The proposed amplifiers were compared to the typical Class-BD configuration, using the optimal NBDD modulation with respect to audio performance of the Differential-Mode (DM) and Common-Mode (CM) outputs. Basic SPICE simulations and experimental studies have shown that the proposed Class-BD amplifiers have similar audio performance to the prototype with the optimal NBDD modulation scheme, while at the same time having a balanced constant voltage CM output, thus eliminating the main contributor to radiation emission. As a result, the filtering of the DM output signals can be greatly simplified, while the filtering of the CM output signals can be theoretically eliminated. Practically, due to the timing errors added by the gate drivers, spikes are generated at the CM output, which are very easy to filter out by the reduced LC output filter, even at very low L.

The paper proposes an original single-phase transformerless three-level (S-PT) photovoltaic (PV) inverter in the cascade H bridge (CHB) configuration. The DC-link voltage of the inverter is created by two serial voltage sources with a voltage twice as low as the DC-link voltage. An appropriate V_CC DC-link voltage is generated by a two-phase DC-DC boost converter, fed from the string panel output at a level determined by the maximum power point tracking (MPPT) algorithm. Two symmetrical sources with V_CC/2 are formed by a divider of two series-connected capacitors of large and the same capacitance. The common mode (CM) voltage of the proposed inverter is constant, and the voltage stresses across all switches, diodes and gate drive circuits are half of the DC-link voltage. The principles of operation of the S-PT inverter, an implementation of a complete gate control system with galvanic isolation for all IGBTs, are also presented. The proposed inverter topologies have been implemented using high-speed IGBTs and simulated in PSPICE, as well as being experimentally validated.