Partial photodetachment and photoionization cross sections corresponding to highly excited residual atoms or ions are shown analytically to mirror one another in the neighborhood of a resonance. More precisely, any two groupings of partial cross sections are shown here to have components whose variations with energy near a resonance are equal in magnitude and opposite in direction. This work extends an analysis of Starace [Phys. Rev. A 16, 231 (1977)] for the behavior of partial cross sections near a resonance to the case when the ${\rho }^2$ parameter of Fano and Cooper [Phys. Rev. 137, A1364 (1965)] tends to zero.

Layout migration is a fast methodology to generate the required layout for given circuits with different device attributes or different technology. By keeping the original layout topology, the previous design experience can help to keep the circuit performance. However, routing preservation is often not mentioned in previous layout migration techniques, which requires a complete rerouting to break the original style. Pan et al. (2015) proposed a topological slicing tree and a constrained delaunay triangulation (CDT) model to keep the routing style during migration. However, this approach may incur some missing nets after migration, which still requires tedious manual works to fix those nets. In this article, we propose a sequence pair (SP)-based placement migration methodology and a novel Cartesian detection line (CDL) model to preserve the routing styles in original layouts. By using the proposed approach, the routability information and routing behaviors can be preserved during layout migration. In order to prevent from missing nets, several refinement techniques are also proposed to fix unreasonable routing nets due to block displacement. In the experiments, the missing nets after migration can be reduced to almost zero with the proposed CDL model, which greatly reduces the extra design efforts.

In recent years, In-RRAM Computing (IRC) has been a promising technique for deep neural network (DNN) applications. Combined with the proper pruning technique, the cost and energy of DNN computation can be further reduced. However, IRC often suffers from accuracy issues due to the nonideal effects in RRAM arrays, such as the sneak path and IR-drop, as well as its data allocation. To mitigate those nonideal effects, network retraining with extra error injection is often adopted to alleviate the accuracy degradation of IRC designs in the real environment. Conventional random disturbance and equation-based approaches did not consider the data allocation issue, which may incur larger errors for the sparse matrix generated by data pruning techniques. In this article, a fast and accurate IR-drop model is proposed to reflect the data-dependent effects, which is able to offer accurate error injection in the DNN training phase with sparse matrixes. As shown in the experimental results, the proposed simple model is successfully integrated into the network retraining flow with little overhead, which helps to alleviate the computation errors of IRC designs in the real environment.

In recent years, Computing In-Memory (CIM) technology has been proposed to solve the bottleneck of data movement in AI edge designs. In-RRAM Computing (IRC) is a popular architecture due to its low leakage current and high density. However, to integrate some simple computation in memory, the IRC designs often adopt analog operations, which bring new issues to the computation accuracy. In order to speed up the verification of computation results, an accurate behavioral model for the RRAM crossbar array and the peripheral circuits with non-ideal effects is proposed. By using the proposed behavioral model, we build a hierarchical simulation framework for the IRC system to provide runtime errors for circuit design optimization and CNN training. As shown in the experimental results, the simulation accuracy of the IRC system is greatly improved by considering the contribution from peripheral circuits, but the simulation time can be reduced from several hours to 1 minute. The error-aware CNN training with the proposed models efficiently improves the CNN inference accuracy in real applications, which solves the accuracy and efficiency issues in traditional approaches.

In order to take full advantage of chiplet-based system synthesis methodology for HPC and AI applications in high-bandwidth memory, die-to-die designs interconnect need an overhaul breakthrough. The major reason lies in the strengthening technologies: offset-via and teardrop. They need special care in order to enhance reliability and manufacturability. Moreover, conventional signal integrity problems are required to pay attention as well. In this work, by empirical offset-via and layer assignment, we first make sure the optimized routing resources on all the redistribution layers. Then we devise an S-route detailed routing to prevent the detour and to reduce the rip-up and re-route iterations. Results show that we achieved total wire length reduction by 7% on average and total usage of RDLs by nearly 50%, compared with combined SOTA approaches.