In recent years, Japan’s agricultural industry has faced a number of challenges, including a decline in production due to a decrease in farmland area, a shortage of labor due to a decrease in the number of producers, and an aging population. Therefore, in recent years, smart agriculture using robots and IoT has been studied. A caliper is often used to analyze the growth of tomatoes in a plant factory, but this method may damage the stems and is also hard on the measurer. We developed a system that detects them through image analysis and measures the thickness of stems and the length between flower clusters and growing points. The camera device developed in this study costs about USD 150 and once installed, it does not need to be moved unless it malfunctions. The camera device reduces the effort required to analyze crop growth by about 80%.

The RISC-V core, which supports simultaneous multithreading (SMT) on a heterogeneous virtual engine architecture, has been implemented. In the architecture, multiple types of engines specialized for different purposes are included. The RISC-V SMT core has the advantage of allowing multiple threads to execute simultaneously with a lower cost than that of simply using multiple cores. The RISC-V core supports operations of other engines under the SMT mechanism to be installed in “Chichibu,” which has been developed by ArchiTek Co., LTD as a multicore chip for edge artificial intelligence. In this implementation, we have reduced the hardware resource usage to less than half that of the previous implementation and exceeded the operating frequency of 100 MHz. In addition, the instructions per clock cycle (IPC) has been improved by approximately 66% using SMT.

Semantic segmentation using neural networks (NNs) has significant potential for weed detection in agricultural fields. However, conventional datasets captured from aerial perspectives often fail to detect weeds that are either hidden beneath crops or submerged in water. This study proposes a method for accurately detecting weed pixels through ensemble learning-based semantic segmentation, using forward-facing images captured by a camera mounted on an aquatic drone navigating between rice plants. We also present a paddy field weed image dataset constructed to train the NN models. Multiple semantic segmentation models were trained, compared, and evaluated, achieving a weed intersection over union (IoU) of 0.441, mean IoU (mIoU) of 0.706, and pixel accuracy of 0.971.

This paper presents a support function for MPI derived datatypes on DIMMnet-3 network interface with multi-banked extended memory, which is under development. Semi-hardwired derived datatype communication based on RDMA with hardwired gather and scatter is proposed. This mechanism and MPI using it are implemented and validated on DIMMnet-2 which is a former prototype operating on DDR DIMM slot. The performance of gather or scatter transfer of 8byte elements with large interval by using vector commands of DIMMnet-2 is 6.8 compared with software on a host. Proprietary benchmark of MPI derived datatype communication for transferring a submatrix corresponding to a narrow HALO area is executed. Observed bandwidth on DIMMnet-2 is far higher than that for similar condition with VAPI based MPI implementation on Infniband, even though poorer CPU and motherboard are used.

In recent years, demand for data-parallel processing has been growing, and this parallelism often appears in AI processes. One method to accelerate these processes is using DSA, domain-specific architecture. A common data transfer method on DSA is DMA, which is direct memory access. There are several studies on DMA-based accelerators. However, few studies focus on data transfer methods. In this paper, a vector register-sharing mechanism has been proposed as a new data transfer method. Our proposed mechanism is named "SHAVER". In this mechanism, a part of vector registers is directly shared with an accelerator. An open-source RISC-V vector co-processor is used to evaluate the mechanism's potential. It has been implemented on an FPGA and a simulator for the evaluations. The results indicate the possibility of the proposal mechanism to achieve a maximum of 8.38% speedup over DMA transfer.