Robert Rieger

Prof. Dr. Robert Rieger

Faculty of Engineering, Kiel University, D-24143 Kiel, Germany
orcid

Research Focus & Metrics

Academic Career Length

25Years (2002-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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19 December 2006 in IEEE Transactions on Neural Systems and Rehabilitation Engineering
Verified
Journal Article
Closed access
Robert RiegerRobert Rieger
Robert Rieger
MSMartin Schuettler
Martin Schuettler
DPDipankar Pal
Dipankar Pal
CCChris Clarke
Chris Clarke
PLPeter Langlois
Peter Langlois
NDNick Donaldson
Nick Donaldson
In this paper, we describe the design and testing of a system for recording electroneurographic signals (ENG) from a multielectrode nerve cuff (MEC). This device, which is an extension of the conventional nerve signal recording cuff, enables ENG to be classified by action potential velocity. In addition to electrical measurements, we provide preliminary in vitro data obtained from frogs that demonstrate the validity of the technique for the first time. Since typical ENG signals are extremely small, on the order of 1 1 muV, very low-noise, high-gain amplifiers are required. The ten-channel system we describe was realized in a 0.8 mum CMOS technology and detailed measured results are presented. The overall gain is 10 000 and the total input-referred root mean square (rms) noise in a bandwidth 1 Hz-5 kHZ is 291 nV. The active area is 12 mm2 and the power consumption is 24 mW from plusmn2.5 V power supplies

25 October 2004 in IEEE Journal of Solid-State Circuits
Verified
Journal Article
Closed access
Robert RiegerRobert Rieger
Robert Rieger
ADA. Demosthenous
A. Demosthenous
JTJ. Taylor
J. Taylor
This paper describes a micropower CMOS integrator with an extremely large time constant for use in a variety of low-frequency signal processing applications. The specific use of the integrator in an implantable biomedical integrated circuit is described. The integrator is based on the OTA-C approach and a very small transconductance of 100 pA/V was achieved by cascading a short chain of transconductance-transimpedance stages. The time constant of the integrator is tunable between about 0.2 and 10 s, and any offset voltages at the output terminal can be trimmed out. The circuit was fabricated in a 0.8-/spl mu/m CMOS process, dissipates 230 nW from /spl plusmn/1.5 V power supplies (excluding the bias circuitry and output buffers) and has a core area of 0.1 mm/sup 2/. The integrator offers superior performance in terms of power consumption, die area and time constant when compared to previously published work.

12 August 2008 in Medical & Biological Engineering & Computing
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Journal Article
Closed access
PDF file
NDN. Donaldson
N. Donaldson
Robert RiegerRobert Rieger
Robert Rieger
MSM. Schuettler
M. Schuettler
JTJ. Taylor
J. Taylor

10 February 2011 in IEEE Transactions on Biomedical Circuits and Systems
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Journal Article
Closed access
Robert RiegerRobert Rieger
Robert Rieger
This paper presents a low-noise front-end amplifier with configurable gain, targeting the recording of small signals, such as the electrocardiogram (ECG) or electroneurogram (ENG). The circuit consists of a continuous-time input stage using lateral bipolar transistors realized in complementary metal-oxide semiconductor (CMOS) technology followed by a switched-capacitor integrating stage. The voltage gain is adjustable by varying the phase delay between two system clocks. Simulated and measured results for a chip fabricated in 0.35-μm CMOS technology are reported. The amplifier occupies an active area of 0.064 mm2, yields a nominal gain of 630 V/V with more than a 50-dB tuning range, less than 16 nVrms/√Hz input noise and a common-mode rejection of more than 97 dB. Its power consumption is 280 μW with a ±1.5-V supply.

19 December 2013 in IEEE Transactions on Biomedical Circuits and Systems
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Journal Article
Closed access
STShin-Lian Teng
Shin-Lian Teng
Robert RiegerRobert Rieger
Robert Rieger
YLYu-Bin Lin
Yu-Bin Lin
This paper presents a configurable CMOS integrated circuit front-end for the recording of a wide range of biopotentials (ExG). The system offers a choice between a single-differential or double-differential recording channel topology, wide continuously adjustable gain range (37-66 dB), selectable CMOS or BJT input stages, offset compensation, differential and buffered single-ended voltage output. Measured results from a prototype manufactured in 0.35 μm CMOS technology are presented. Practical recording examples of the electrocardiogram (ECG) and electromyogram (EMG) confirm its operation. The chip consumes between 110 and 324 μW depending on configuration, occupies a core area of 0.16 mm 2 , achieves a CMRR > 97 dB, and 21 nV/√Hz input-referred noise. The chip is suited for combination with a microcontroller in long-term wearable physiological sensing applications.

1 July 2004 in Medical Engineering & Physics
Verified
Journal Article
Closed access
Robert RiegerRobert Rieger
Robert Rieger
JTJ Taylor
J Taylor
ECE Comi
E Comi
NDN Donaldson
N Donaldson
MRM Russold
M Russold
JJJ.C Jarvis
J.C Jarvis
Information extracted from whole-nerve electroneurograms, recorded using electrode cuffs, can provide signals to neuroprostheses. However, the amount of information that can be extracted from a single tripole is limited. This communication demonstrates how previously unavailable information about the direction of action potential propagation and velocity can be obtained using a multi-electrode cuff and that the arrangement acts as a velocity-selective filter. Results from in vitro experiments on frog nerves are presented.