The inductor was primarily developed on a low-voltage CMOS tunable active inductor (CTAI) for radar applications. Technically, the factors to be considered for VCO design are power consumption, low silicon area, high frequency with reasonable phase noise, an immense quality (Q) factor, and a large frequency tuning range (FTR). We used CMOS tunable active inductor (TAI) topology relying on cascode methodology for 24 GHz frequency operation. The newly configured TAI adopts the additive capacitor $\left(C_{ad}\right)$ with the cascode approach, and in the subthreshold region, one of the transistors functions as the TAI. The study, simulations, and measurements were performed using 65nm CMOS technology. The assembled circuit yields a spectrum from 21.79 to 29.92 GHz output frequency that enables sustainable platforms for K-band and Ka-band operations. The proposed design of TAI demonstrates a maximum Q-factor of 6825, and desirable phase noise variations of −112.43 and −133.27 dBc/Hz at 1 and 10 MHz offset frequencies for the VCO, respectively. Further, it includes enhanced power consumption that varies from 12.61 to 23.12 mW and a noise figure (NF) of 3.28 dB for a 24 GHz radar application under a low supply voltage of 0.9 V.

Vehicular visible light communication is known as a promising way of inter-vehicle communication. Vehicular VLC can ensure the significant advancement of safety and efficiency in traffic. It has disadvantages, such as unexpected glare on drivers in moving conditions, i.e., non-line-of-sight link at night. While designing a receiver, the most important factor is to ensure the optimal quality of the received signal. Within this context, to achieve an optimal communication quality, it is necessary to find the optimal maximum signal strength. Hereafter, a new receiver design is focused on in this paper at the circuit level, and a novel micro genetic algorithm is proposed to optimize the signal strength. The receiver can calculate the SNR, and it is possible to modify its structural design. The micro GA determines the alignment of the maximum signal strength at the receiver point rather than monitoring the signal strength for each angle. The results showed that the proposed scheme accurately estimates the alignment of the receiver, which gives the optimum signal strength. In comparison with the conventional GA, the micro GA results showed that the maximum received signal strength was improved by −1.7 dBm, −2.6 dBm for user Location 1 and user Location 2, respectively, which proves that the micro GA is more efficient. The execution time of the conventional GA was 7.1 s, while the micro GA showed 0.7 s. Furthermore, at a low SNR, the receiver showed robust communication for automotive applications.

With the recent growth of the Internet of Things (IoT) and the demand for faster computation, quantized neural networks (QNNs) or QNN-enabled IoT can offer better performance than conventional convolution neural networks (CNNs). With the aim of reducing memory access costs and increasing the computation efficiency, QNN-enabled devices are expected to transform numerous industrial applications with lower processing latency and power consumption. Another form of QNN is the binarized neural network (BNN), which has 2 bits of quantized levels. In this paper, CNN-, QNN-, and BNN-based pattern recognition techniques are implemented and analyzed on an FPGA. The FPGA hardware acts as an IoT device due to connectivity with the cloud, and QNN and BNN are considered to offer better performance in terms of low power and low resource use on hardware platforms. The CNN and QNN implementation and their comparative analysis are analyzed based on their accuracy, weight bit error, RoC curve, and execution speed. The paper also discusses various approaches that can be deployed for optimizing various CNN and QNN models with additionally available tools. The work is performed on the Xilinx Zynq 7020 series Pynq Z2 board, which serves as our FPGA-based low-power IoT device. The MNIST and CIFAR-10 databases are considered for simulation and experimentation. The work shows that the accuracy is 95.5% and 79.22% for the MNIST and CIFAR-10 databases, respectively, for full precision (32-bit), and the execution time is 5.8 ms and 18 ms for the MNIST and CIFAR-10 databases, respectively, for full precision (32-bit).

This article introduces a novel method for extracting crucial parameters from a fifth-generation (5G) CMOS power amplifier (PA) operating at 24 GHz. The proposed method, micro-genetic algorithm artificial neural network ( $\mu$ -GAANN), presents an innovative synergy between $\mu$ -GA and ANN, enabling the accurate determination of crucial PA (circuit components) parameters. The $\mu$ -GAANN model has a fixed and robust stimulation function ( F SF and R SF). ANNs are trained to approximate the parameter extraction process based on input–output data generated from the $\mu$ -GA. The proposed $\mu$ -GA incorporates the arithmetic crossover and nonuniform mutation; thus, several parameters of the ANN network are tweaked. Moreover, ANN parameters are enhanced by using $\mu$ -GA to achieve an optimal PA design in a shorter period of time. To verify the proposed $\mu$ -GAANN, we have also compared the training time with particle swarm optimization (PSO) employed in ANN, i.e., PSOANN. Besides, a derivative superposition (DS) linearization technique is used in the PA circuit, along with input load splits (I-LSs) to solve the low input impedance problem of conventional DS. To design a PA, the proposed $\mu$ -GAANN outperforms the traditional feedforward artificial neural networks (TFFANN). Using $\mu$ -GAANN, the PA’s simulated S21 is 25 dB, while the measured S21 is 21.2 dB. With traditional TFFANN, we observe a simulated gain of 24.1 dB for the PA. We achieved a simulated gain of 23.2 dB of the PA without using ANNs. The measured results of the $P$ sat and PAE of the PA with $\mu$ -GAANN are 9.8 dBm and 32.1%, respectively. Also, a measured PA achieves a high third-order-input-intercept point (IIP3) of 14.1 dBm. The core chip area of the PA is 0.35 mm ² .

This paper presents a high conversion gain and highly linearised up‐conversion mixer designed in 65 nm CMOS process, which translates intermediate frequency of 2.4 GHz and local oscillator frequency of 21.6–24 GHz in radio frequency. In the proposed mixer, the tranconductance stage consists of a common source route with neutralisation technique and dual capacitive cross coupled‐common gate route to achieve high linearity and stability. In addition, it also includes dual negative resistance switches with improved inter‐stage matching network to enhance the conversion gain and to decrease the noise figure. The mixer achieves the conversion gain of 4.7 dB, the measured output 1‐dB compression point of 0.41 dBm and noise figure of 3.8 dB at 24 GHz. In an automotive radar application, the proposed mixer showed a high conversion gain, an excellent output 1‐dB and a low noise figure with power consumption of approximately 5.2 mW at a 1.2 V supply.