IGZO thin films can be used as active layers of thin-film transistors and have been widely studied. However, amorphous indium gallium zinc oxide (IGZO) fabricated at room temperature is vulnerable in subsequent manufacturing processes, such as etching and sputtering; this limits IGZO thin film transistors’ (TFTs) use in commercial products. In this paper, we prepared a c-axis crystallized IGZO thin film by Radio Frequency (RF) sputtering at 180 °C, with a 50% O₂ ratio and 110 W power. XRD images show that the crystallized film has an obvious diffraction peak near 31°, and the spacing between the crystal surfaces was calculated to be ≈0.29 nm. The HRTEM map confirmed the above results. The stability of IGZO thin films was investigated by etching them with an acid solution. The crystalline IGZO films exhibited better acid corrosion resistance, and their anticorrosion performance was 74% higher than that of amorphous IGZO (a-IGZO) films, indicating the crystalline IGZO film can provide more stable performance in applications.

The accurate measurement of the thermal conductivity in a wide range of semiconductors is of great importance for applications like power electronic devices, which is, however, quite challenging. Current measurement methods suffer from limited measurement range, non-accuracy, complexity, etc. We report in this work an effective in situ method for thermal conductivity measurement based on laser-excited Raman spectroscopy, which has the advantages of non-contact, non-destructive, facile preparation, easy operation, and the capability of a large measurement range. The critical relationship parameters correlating Raman peak shifts and temperature change can be extracted by monitoring and fitting the Raman peak movement at different temperatures. Here, the laser with the micrometer scale spot serves as a Raman scattering source and a heat source for the samples. The thermal conductivity of Si, SiC, polycrystalline diamond, and single crystalline diamond at room temperature was determined to be 140.2 ± 14.4, 414.7 ± 26.2, 1372.3 ± 229.0, and 1734.9 ± 280.6 W/(m K), respectively, which are in good agreement with the theoretical prediction. The temperature distribution of the samples was simulated by the finite element method, which confirms the experimental data. These results highlight the feasibility, reliability, and versatility of Raman spectroscopy for measuring semiconductor materials, particularly those with high thermal conductivity. This is of great interest for exploring semiconductor physics and practical applications like power electronic devices.

We proposed an effective strategy involving a differential distribution of voltages among dynodes to significantly enhance the gain and stability of discrete dynode electron multipliers (DEMs) under continuous electron bombardment. The effects of the differential voltage distribution on the DEM performance were systematically investigated through experiments and numerical simulations. The differential voltage distribution of 7:7:7:7:7:5:5:5:5 enables the DEM to achieve a gain of 3.4 $\times$ 10 $^{\text{4}}$ , representing a substantial increase by 2.1 times at an operating voltage of 1200 V, and the operating voltage at a gain of 10 $^{\text{6}}$ to be reduced to 1949 V with a decrease of 186 V in comparison to the traditional uniform voltage distribution of 1:1:1:1:1:1:1:1:1. The gain enhancement is closely related to the increased average secondary electron emission (SEE) coefficients of dynodes D2–D6 and the improved electron collection efficiencies of dynodes D3 and D6. Additionally, the differential voltage also reduced the gain decay rate to 16.7%/mC, reflecting a decrease of 14.8% due to the suppression of SEE degradations in dynodes D7–D9, which can be attributed to their lower average SEE coefficients. Overall, the proposed strategy of differential voltage distribution, characterized by higher voltages among earlier dynodes and lower voltages among latter dynodes, presents a novel and universal approach for optimizing the structure of electron multipliers, addressing the need for highly sensitive and reliable detection of ultraweak or even single charged particles.

Carbon nanotube field-effect transistors (CNTFETs) have been considered a strong candidate for post-Si era electronics due to the virtues of higher speed, lower power consumption, and multiple functionalities. The interface analysis based on the top gate structure has made little progress and lacks a reliable charge trap characterization model suitable for carbon tube devices. Quantitative extraction and analysis of the interface state are crucial for the integration of top-gate devices. Herein, a 5 nm thick Y₂O₃ thin film was selected as the gate dielectric layer in the top-gate CNTFETs device, and a post-annealing process in air ambience was utilized to optimize the Y₂O₃-CNT interface. A series of device performance evaluation results indicated that the post-annealing process in air ambience can effectively improve the on-state current and reduce the threshold voltage and subthreshold swing of the device, which are derived from diffusion of oxygen atom in the Y₂O₃ layer and optimization of the interface of Y₂O₃-CNT. Specifically, the maximum mobility, subthreshold swing, and threshold voltage are calculated to be 29 cm²/V s, 103 mV/dec, and −0.1 V, respectively, and the interface state density is reduced from 2.68 × 10¹² to 1.51 × 10¹² cm⁻² in the gate insulator. These results not only are important to understand the dielectric impact on CNTFET devices but also are useful for future materials’ development and device optimization for high-performance CNT-based electronics.