Mariano Scazzariello

Mr. Mariano Scazzariello


Research Focus & Metrics

Academic Career Length

6Years (2021-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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13 June 2024 in Proceedings of the ACM on Networking
Verified
Journal Article
Open access
CWChangjie Wang
Changjie Wang
MSMariano Scazzariello
Mariano Scazzariello
AFAlireza Farshin
Alireza Farshin
SFSimone Ferlin
Simone Ferlin
DKDejan Kostic
Dejan Kostic
MCMarco Chiesa
Marco Chiesa
This paper explores opportunities to utilize Large Language Models (LLMs) to make network configuration human-friendly, simplifying the configuration of network devices & development of routing algorithms and minimizing errors. We design a set of benchmarks (NetConfEval) to examine the effectiveness of different models in facilitating and automating network configuration. More specifically, we focus on the scenarios where LLMs translate high-level policies, requirements, and descriptions (i.e., specified in natural language) into low-level network configurations & Python code. NetConfEval considers four tasks that could potentially facilitate network configuration, such as (i) generating high-level requirements into a formal specification format, (ii) generating API/function calls from high-level requirements, (iii) developing routing algorithms based on high-level descriptions, and (iv) generating low-level configuration for existing and new protocols based on input documentation. Learning from the results of our study, we propose a set of principles to design LLM-based systems to configure networks. Finally, we present two GPT-4-based prototypes to (i) automatically configure P4-enabled devices from a set of high-level requirements and (ii) integrate LLMs into existing network synthesizers.

27 November 2023 in Proceedings of the ACM on Networking
Verified
Journal Article
Open access
TCTommaso Caiazzi
Tommaso Caiazzi
MSMariano Scazzariello
Mariano Scazzariello
MCMarco Chiesa
Marco Chiesa
Key-value data structures are an essential component of today's stateful packet processors such as load balancers, packet schedulers, and more. Realizing key-value data structures entirely in the data-plane of an ASIC switch would bring enormous energy savings. Yet, today's implementations are ill-suited for stateful packet processing as they support only a limited amount of flow-state insertions per second into these data structures. In this paper, we present SWITCHAROO, a mechanism for realizing key-value data structures on programmable ASIC switches that supports both high-frequency insertions and fast lookups entirely in the data plane. We show that SWITCHAROO can be realized on ASIC, supports millions of flow-state insertions per second with only limited amount of packet recirculation.

13 January 2025 in IEEE Journal on Selected Areas in Communications
Verified
Journal Article
Closed access
MPMarco Polverini
Marco Polverini
ACAntonio Cianfrani
Antonio Cianfrani
TCTommaso Caiazzi
Tommaso Caiazzi
MSMariano Scazzariello
Mariano Scazzariello
The rise of new applications, such as interactive remote presence, online gaming, and video-assisted remote control of industrial machinery, necessitates enhanced requirements in terms of throughput and delay stability. Many efforts have been made to address these needs, with Deterministic Networking (DetNet) being one such initiative. DetNet aims to guarantee delivery with low latency and minimal jitter, ensuring high reliability and performance for time-sensitive applications. However, DetNet applicability in real-world scenarios is limited due to the need of a lower-layer protocol supporting resource reservation procedures ( e.g. , MPLS), and the lack of publicly available implementations. In this work, we present SRv6 Live-Live, an easy-to-deploy and highly scalable implementation of DetNet functions using the Segment Routing over IPv6 (SRv6) model. The SRv6 Live-Live behavior replicates packets of a selected flow across multiple paths at the ingress of the SRv6 domain and drops redundant replicas at the egress. After discussing insights about the paths’ selection strategy, we provide a SRv6 Live-Live implementation for programmable data planes using P4. We also propose the use of SRv6 Live-Live for best path selection at line rate, in SD-WAN scenarios. The main results obtained in the extensive performance evaluation are that SRv6 Live-Live preserves the throughput in case of congestion and reduces the tail end-to-end delay with a marginal impact on best-effort flows.

30 August 2021 in Future Internet
Verified
Journal Article
Open access
PDF file
MSMariano Scazzariello
Mariano Scazzariello
LALorenzo Ariemma
Lorenzo Ariemma
GBGiuseppe Di Battista
Giuseppe Di Battista
Maurizio PatrignaniMaurizio Patrignani
Maurizio Patrignani
We introduce an open-source, scalable, and distributed architecture, called Megalos, that supports the implementation of virtual network scenarios consisting of virtual devices (VDs) where each VD may have several Layer 2 interfaces assigned to virtual LANs. We rely on Docker containers to realize vendor-independent VDs and we leverage Kubernetes for the management of the nodes of a distributed cluster. Our architecture does not require platform-specific configurations and supports a seamless interconnection between the virtual environment and the physical one. Also, it guarantees the segregation of each virtual LAN traffic from the traffic of other LANs, from the cluster traffic, and from Internet traffic. Further, a packet is only sent to the cluster node containing the recipient VD. We produce several example applications where we emulate large network scenarios, with thousands of VDs and LANs. Finally, we experimentally show the scalability potential of Megalos by measuring the overhead of the distributed environment and of its signaling protocols.

22 April 2024
Verified
Conference Paper
Open access
HGHamid Ghasemirahni
Hamid Ghasemirahni
AFAlireza Farshin
Alireza Farshin
MSMariano Scazzariello
Mariano Scazzariello
MCMarco Chiesa
Marco Chiesa
DKDejan Kostic
Dejan Kostic
Stateful network functions are increasingly used in data centers. However, their scalability remains a significant challenge since parallelizing packet processing across multiple cores requires careful configuration t o avoid compromising the application's semantics or performance. This challenge is particularly important when deploying multiple stateful functions on multi-core servers. This paper proposes FlowMage, a system that leverages Large Language Models (LLMs) to perform code analysis and extract essential information from stateful network functions (NFs) prior to their deployment on a server. FlowMage uses this data to find an efficient configuration of an NF chain that maximizes performance while preserving the semantics of the NF chain. Our evaluation shows that, utilizing GPT-4, FlowMage is able to find and apply optimized configuration when deploying stateful NFs chain on a server, resulting in significant p erformance improvement (up to 11×) in comparison to the default configuration of the system.

18 August 2024 in Proceedings of the ACM on Networking
Verified
Journal Article
Open access
HGHamid Ghasemirahni
Hamid Ghasemirahni
AFAlireza Farshin
Alireza Farshin
MSMariano Scazzariello
Mariano Scazzariello
GMGerald Q. Maguire
Gerald Q. Maguire
DKDejan Kostic
Dejan Kostic
MCMarco Chiesa
Marco Chiesa
Data centers increasingly utilize commodity servers to deploy low-latency Network Functions (NFs). However, the emergence of multi-hundred-gigabit-per-second network interface cards (NICs) has drastically increased the performance expected from commodity servers. Additionally, recently introduced systems that store packet payloads in temporary off-CPU locations (e.g., programmable switches, NICs, and RDMA servers) further increase the load on NF servers, making packet processing even more challenging. This paper demonstrates existing bottlenecks and challenges of state-of-the-art stateful packet processing frameworks and proposes a system, called FAJITA, to tackle these challenges & accelerate stateful packet processing on commodity hardware. FAJITA proposes an optimized processing pipeline for stateful network functions to minimize memory accesses and overcome the overheads of accessing shared data structures while ensuring efficient batch processing at every stage of the pipeline. Furthermore, FAJITA provides a performant architecture to deploy high-performance network functions service chains containing stateful elements with different state granularities. FAJITA improves the throughput and latency of high-speed stateful network functions by ~2.43x compared to the most performant state-of-the-art solutions, enabling commodity hardware to process up to ~178 Million 64-B packets per second (pps) using 16 cores.