It is challenging to train deep spiking neural networks (SNNs) directly due to the difficulties associated with the nondifferentiable neuron model. In this work, an end-to-end learning algorithm based on discrete current-based leaky integrate-and-fire (C-LIF) neuron model and surrogate gradient is proposed to leverage the encoder–decoder network architecture to train deep SNNs directly. The proposed algorithm is capable of learning deep spatiotemporal features relying on current time step only, and several acceleration techniques including backward phase skipping and layerwise FreezeOut are proposed to accelerate the training. Experimental results show that the proposed learning algorithm achieved the classification accuracies of 98.40% and 95.83% on the dynamic neuromorphic data sets MNIST-DVS and DVS-Gestures, respectively, and of 99.58% and 95.97% on static vision data sets MNIST and SVHN, respectively, which are comparable to the existing state-of-the-art results. The training speed was accelerated by up to 49.5% on MNIST and 36.6% on DVS-Gestures with the proposed acceleration techniques while maintaining the same level of accuracy.

Memristors are poised to revolutionize neuromorphic computing and next-generation memory, yet persistent challenges, including stochastic conductance control, limited endurance, and poor scalability, impede their practical adoption. Here, we report a self-rectifying memristor leveraging a GaOx/InOx heterostructure to overcome these barriers. The device demonstrates an ultrahigh rectification ratio and nonlinearity (>107), effectively suppressing sneak currents in passive crossbar arrays. Robust multi-level conductance modulation and cycling stability exceeding 106 cycles are achieved, alongside minimal inter-device variability (σ/μ < 10%) in a 6 × 6 passive array. Critically, it demonstrates dynamic tunability between short-term and long-term plasticity, modulated via pulse number/amplitude, a cornerstone for biologically inspired learning. By implementing the one-bitline pull-up scheme, the design achieves an integration density of 125.1 Tb at a 10% read margin, outperforming state-of-the-art resistive memories. This work establishes oxide heterostructures as a scalable platform for high-density neuromorphic systems, bridging the gap between functional material innovation and hardware-driven machine intelligence.

The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability and the potential in computation application. These properties make them a perfect choice for application in modern computing systems. In this paper, an 8-bit radix-4 non-volatile parallel multiplier is proposed, with improved computational capabilities. The corresponding booth encoding scheme, read-out circuit, simplified Wallace tree, and Manchester carry chain are presented, which help to short the delay of the proposed multiplier. While the presence of RRAM save computational time and overall power as multiplicand is stored beforehand. The area of the proposed non-volatile multiplier is reduced with improved computing speed. The proposed multiplier has an area of 785.2 $\mathsf{\mu }$m${}^2$ with Generic Processing Design Kit 45 nm process. The simulation results show that the proposed multiplier structure has a low computing power at 161.19 $\mathsf{\mu }$W and a short delay of 0.83 ns with 1.2 V supply voltage. Comparative analyses are performed to demonstrate the effectiveness of the proposed multiplier design. Compared with conventional booth multipliers, the proposed multiplier structure reduces the energy and delay by more than 70% and 19%, respectively.

Non-volatile memories (NVM) based computing-in-memory (CIM) architectures suffer from device non-uniformity that causes output deviations. Charge-domain computation mitigates this issue by using capacitor-based charge accumulation but increases area overhead. Earlier approaches reuse the computation array capacitors for Analog-to-Digital Conversion (ADC), yet the conventional structure allows less than half of the capacitors to be reused, limiting both utilization efficiency and conversion precision. The reduced ADC resolution further leads to accuracy degradation in practical neural network applications. To address these challenges, we propose a robust and adaptive 1FeFET-1T-1C CIM macro that reuses nearly all array capacitors within a pipeline SAR ADC architecture, achieving high resolution while maintaining compact area efficiency and lowering latency. Moreover, a charge redistribution mechanism enables analogdomain multi-bit accumulation, eliminating the need for external adder trees and shift circuits. In addition, an adaptive row activation scheme dynamically optimizes the number of active rows based on real-time workload demands. Implemented in a SMIC 55nm PDK, the proposed macro achieves a peak energy efficiency of 97.8 TOPS/W and an area efficiency of 1.153 TOPS/mm². The efficiency is further enhanced under lightweight models, with adaptive row activation achieving up to 51.17% power reduction.

Chiplet-based heterogeneous integration, exemplified by CoWoS packaging, delivers high scalability and performance but introduces critical thermal challenges from power density escalation and inter-chiplet thermal coupling. This study presents a coherent compact thermal network model (CTM) for junction temperature prediction in CoWoS packaging, integrating self-heating effects and thermal interactions across chiplets through a systematic approach. The model incorporates equivalent orthotropic submodels to simplify microstructures such as TSVs, u-bumps, and C4 bumps, while maintaining computational efficiency. A key innovation lies in the novel calculation of coupling thermal resistances between chiplets using analytical solutions for heat spreading in orthotropic materials and superposition principles, enabling the CTM as a coherent system. Validated against COMSOL simulations, the CTM achieves high accuracy (errors ˂4% for primary heat sources) and reduces simulation time by over 99% compared to finite element methods (FEM) and latest related work.