Jianbin Fang

Prof. Dr. Jianbin Fang

orcid

Research Focus & Metrics

Academic Career Length

18Years (2009-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 September 2011
Verified
Conference Paper
Closed access
Jianbin FangJianbin Fang
Jianbin Fang
AVAna Lucia Varbanescu
Ana Lucia Varbanescu
HSHenk Sips
Henk Sips
This paper presents a comprehensive performance comparison between CUDA and OpenCL. We have selected 16 benchmarks ranging from synthetic applications to real-world ones. We make an extensive analysis of the performance gaps taking into account programming models, ptimization strategies, architectural details, and underlying compilers. Our results show that, for most applications, CUDA performs at most 30% better than OpenCL. We also show that this difference is due to unfair comparisons: in fact, OpenCL can achieve similar performance to CUDA under a fair comparison. Therefore, we define a fair comparison of the two types of applications, providing guidelines for more potential analyses. We also investigate OpenCL's portability by running the benchmarks on other prevailing platforms with minor modifications. Overall, we conclude that OpenCL's portability does not fundamentally affect its performance, and OpenCL can be a good alternative to CUDA.

1 December 2014 in Journal of Computational Physics
Verified
Journal Article
Closed access
CXChuanfu Xu
Chuanfu Xu
XDXiaogang Deng
Xiaogang Deng
LZLilun Zhang
Lilun Zhang
Jianbin FangJianbin Fang
Jianbin Fang
GWGuangxue Wang
Guangxue Wang
XCXinghua Cheng
Xinghua Cheng

31 July 2020 in CCF Transactions on High Performance Computing
Verified
Journal Article
Closed access
PDF file
Jianbin FangJianbin Fang
Jianbin Fang
CHChun Huang
Chun Huang
TTTao Tang
Tao Tang
Zheng WangZheng Wang
Zheng Wang

1 October 2018 in Frontiers of Information Technology & Electronic Engineering
Verified
Journal Article
Closed access
PDF file
XLXiang-Ke Liao
Xiang-Ke Liao
KLKai Lu
Kai Lu
CYCan-Qun Yang
Can-Qun Yang
JLJin-Wen Li
Jin-Wen Li
YYYuan Yuan
Yuan Yuan
JSJie Shen
Jie Shen
High-performance computing (HPC) is essential for both traditional and emerging scientific fields, enabling scientific activities to make progress. With the development of high-performance computing,...

22 March 2014
Verified
Conference Paper
Open access
Jianbin FangJianbin Fang
Jianbin Fang
HSHenk Sips
Henk Sips
LZLiLun Zhang
LiLun Zhang
CXChuanfu Xu
Chuanfu Xu
YCYonggang Che
Yonggang Che
AVAna Lucia Varbanescu
Ana Lucia Varbanescu
Based on Intel's Many Integrated Core (MIC) architecture, Intel Xeon Phi is one of the few truly many-core CPUs - featuring around 60 fairly powerful cores, two levels of caches, and graphic memory, all interconnected by a very fast ring. Given its promised ease-of-use and high performance, we took Xeon Phi out for a test drive. In this paper, we present this experience at two different levels: (1) the microbenchmark level, where we stress "each nut and bolt" of Phi in the lab, and (2) the application level, where we study Phi's performance response in a real-life environment. At the microbenchmarking level, we show the high performance of five components of the architecture, focusing on their maximum achieved performance and the prerequisites to achieve it. Next, we choose a medical imaging application (Leukocyte Tracking) as a case study. We observed that it is rather easy to get functional code and start benchmarking, but the first performance numbers can be far from satisfying. Our experience indicates that a simple data structure and massive parallelism are critical for Xeon Phi to perform well. When compiler-driven parallelization and/or vectorization fails, programming Xeon Phi for performance can become very challenging.

29 July 2019 in IEEE Transactions on Parallel and Distributed Systems
Verified
Journal Article
Closed access
ZCZhaoyun Chen
Zhaoyun Chen
WQWei Quan
Wei Quan
MWMei Wen
Mei Wen
Jianbin FangJianbin Fang
Jianbin Fang
JYJie Yu
Jie Yu
LLLei Luo
Lei Luo
Deep learning (DL) has been widely adopted in various domains of artificial intelligence (AI), achieving dramatic developments in industry and academia. Besides giant AI companies, numerous small and medium-sized enterprises, institutes, and universities (EIUs) have focused on the research and development (R&D) of DL. Considering the high cost of datacenters and high performance computing (HPC) systems, EIUs prefer adopting off-the-shelf GPU clusters as a DL R&D platform for multiple users and developers to process diverse DL workloads. In such scenarios, the scheduling of multiple DL tasks on a shared GPU cluster is both significant and challenging in terms of efficiently utilizing limited resources. Existing schedulers cannot predict the resource requirements of diverse DL workloads, leading to the under-utilization of computing resources and a decline in user satisfaction. This paper proposes GENIE, a QoS-aware dynamic scheduling framework for a shared GPU cluster, which achieves users' QoS guarantee and high system utilization. In accordance with an exhaustive characterization, GENIE analyzes the key factors that affect the performance of DL tasks and proposes a prediction model derived from lightweight profiling to estimate the processing rate and response latency for diverse DL workloads. Based on the prediction models, we propose a QoS-aware scheduling algorithm to identify the best placements for DL tasks and schedule them on the shared cluster. Experiments on a GPU cluster and large-scale simulations demonstrate that GENIE achieves a QoS-guarantee percentage improvement of up to 67.4 percent and a makespan reduction of up to 28.2 percent, compared to other baseline schedulers.