Energy consumption has become dominant issue for wireless internet of things (IoT) networks with battery-powered nodes. The prevailing mechanism allowing to reduce energy consumption is duty-cycling. In this technique the node sleeps most of the time and wakes up only at selected moments to extend the lifespan of nodes up to 5–10 years. Unfortunately, the scheduled duty-cycling technique is always a trade-off between energy consumption and delay in delivering data to the target node. The delay problem can be alleviated with an additional wake-up radio (WuR) channel. In the paper we present original power consumption models for various duty-cycling schemes. They are the basis for checking whether WuR approach is competitive with scheduled duty-cycling techniques. We determine the maximum energy level that an additional wake-up radio can consume to become a reasonable alternative of widely used duty-cycling techniques for typical IoT networks.

It is hard to shield systems effectively from transient faults (fault avoidance techniques). So some other means must be employed to assure appropriate levels of transient fault tolerance (insensitivity to transient faults). They are based on fault-masking and fault recovery ideas. Having analyzed this problem, the author identifies critical design points and outlines some practical solutions that refer to efficient on-line detectors (detecting errors during the system operation) and error handling procedures. This framework provides a basis for understanding transient fault problems in digital systems. It can be helpful in selecting optimum techniques to mask or eliminate transient fault effects in developed systems.

An approach is presented to the online detection of control flow errors caused by transient and intermittent faults in microprocessor systems. It is based on the idea of signatured instruction streams. Signatures are embedded into the program memory using the monitored processor instructions. Compared with existing techniques, the presented approach is universal and can be easily implemented using off-the-shelf programmable array logic and LCA circuits. The hardware overhead ranges from one to several chips for microprocessors with 8-bit and 16-bit data buses. Program memory overhead is 10-20% and quite often no extra memory chip is required. A special software module has been developed to embed signatures and checkpoints into application programs.