Schizophrenia is a multifaceted chronic psychiatric disorder that affects the way a human thinks, feels, and behaves. Inevitably, natural randomness exists in the psychological perception of schizophrenic patients, which is our primary source of inspiration for this research because true randomness is the indubitably ultimate valuable resource for symmetric cryptography. Famous information theorist Claude Shannon gave two desirable properties that a strong encryption algorithm should have, which are confusion and diffusion in his fundamental article on the theoretical foundations of cryptography. Block encryption strength against various cryptanalysis attacks is purely dependent on its confusion property, which is gained through the confusion component. In the literature, chaos and algebraic techniques are extensively used to design the confusion component. Chaos- and algebraic-based techniques provide favorable features for the design of the confusion component; however, researchers have also identified potential attacks on these techniques. Instead of existing schemes, we introduce a novel methodology to construct cryptographic confusion component from the natural randomness, which are existing in the psychological perception of the schizophrenic patients, and as a result, cryptanalysis of chaos and algebraic techniques are not applicable on our proposed technique. The psychological perception of the brain regions was captured through the electroencephalogram (EEG) readings during the sensory task. The proposed design passed all the standard evaluation criteria and validation tests of the confusion component and the random number generators. One million true random bits are assessed through the NIST statistical test suite, and the results proved that the psychological perception of schizophrenic patients is a good source of true randomness. Furthermore, the proposed confusion component attains better or equal cryptographic strength as compared to state-of-the-art techniques (2020 to 2021). To the best of our knowledge, this nature of research is performed for the first time, in which psychiatric disorder is utilized for the design of information security primitive. This research opens up new avenues in cryptographic primitive design through the fusion of computing, neuroscience, and mathematics.

This paper proposes a novel hardware design for a compact crypto processor devoted to elliptic-curve point multiplication over $GF\left(2^{233}\right)$. We focus on minimizing hardware usage, which we obtain using an iterative bit–serial finite field modular multiplier for polynomial coefficient multiplication. The same multiplier is also used for modular squares and inversion computations, further optimizing the hardware footprint. Our design offers flexibility by permitting users to load different curve parameters and secret keys while keeping a low-area hardware design. To efficiently generate the control signals, we utilize a finite-state-machine-based controller. We have implemented the proposed crypto processor on Virtex-6 and Virtex-7 FPGA devices, and we have evaluated its performance at clock frequencies of 100, 50, and 10 MHz. Specifically, for one point multiplication computation on Virtex-7 FPGA, our crypto processor uses 391 slices, attains a maximum frequency of 161 MHz, has a latency of 4.45 ms, and consumes 77 mW of power. These results, along with a comparison to state-of-the-art designs, clearly demonstrate the practicality of our crypto processor for applications requiring efficient and compact cryptographic computations.

This study synthesizes peer-reviewed literature to examine how blockchain technology supports Automated Project Governance (APG), focusing on the organizational, institutional, and human conditions under which potential governance contribution is realized. A systematic literature review was conducted in accordance with PRISMA 2020 guidelines, yielding twenty-one empirically and conceptually grounded studies. Screening reliability was strengthened through independent dual screening at the full-text eligibility stage (inter-rater κ = 0.81). Seven blockchain-enabled governance mechanisms are synthesized and comparatively assessed in terms of evidentiary support and research maturity, suggesting that blockchain’s decentralized and immutable architecture may support transparency, accountability, and coordination when embedded within appropriate governance arrangements, but these benefits do not arise automatically from technological adoption. The synthesis further identifies enabling conditions, including stakeholder acceptance, organizational governance readiness, and institutional alignment, and maps explicit research gaps for each mechanism to guide future empirical inquiry. By grounding the synthesis in the Technology Acceptance Model and Institutional Theory, the study provides a literature-derived, socio-technical framework for understanding blockchain adoption in APG and offers governance-oriented insights for organizations and policymakers.

The Internet of Things (IoT) constitutes a digitally integrated network of intelligent devices equipped with sensors, software, and communication capabilities, facilitating data exchange among a multitude of digital systems via the Internet. Despite its pivotal role in the software development life-cycle (SDLC) for ensuring software quality in terms of both functional and non-functional aspects, testing within this intricate software–hardware ecosystem has been somewhat overlooked. To address this, various testing techniques are applied for real-time minimization of failure rates in IoT applications. However, the execution of a comprehensive test suite for specific IoT software remains a complex undertaking. This paper proposes a holistic framework aimed at aiding quality assurance engineers in delineating essential testing methods across different testing levels within the IoT. This delineation is crucial for effective quality assurance, ultimately reducing failure rates in real-time scenarios. Furthermore, the paper offers a mapping of these identified tests to each layer within the layered framework of the IoT. This comprehensive approach seeks to enhance the reliability and performance of IoT-based applications.

This article proposes a flexible hardware accelerator optimized from a throughput and area point of view for the computationally intensive part of elliptic curve cryptography. The target binary fields, defined by the National Institute of Standards and Technology, are $GF\left(2^{163}\right)$, $GF\left(2^{233}\right)$, $GF\left(2^{283}\right)$, $GF\left(2^{409}\right)$, and $GF\left(2^{571}\right)$. For the optimization of throughput, the proposed accelerator employs a digit-parallel multiplier. The size of the digit is 41 bits. The proposed accelerator has reused the multiplication and squaring circuit for area optimization to compute modular inversions. Flexibility is included using three additional buffers on top of the proposed accelerator architecture to load different input parameters. Finally, a dedicated controller is used to optimize control signal handling. The architecture is modeled using Verilog and implemented up to the post-place-and-route level on a Xilinx Virtex-7 field-programmable gate array. The area utilization of our accelerator in slices is 1479, 1998, 2573, 3271, and 4469 for $m=163$ to 571. The time needed to perform one-point multiplication is 7.15, 10.60, 13.26, 20.96, and 30.42 μs. Similarly, the throughput over area figures for the same key lengths are 94.56, 47.21, 29.30, 14.58, and 7.35. Consequently, achieved results and a comprehensive performance comparison show the suitability of the proposed design for constrained environments that demand throughput/area-efficient implementations.