Recent advances in power converter applications with highly demanding control goals require the efficient implementation of superior control strategies. However, the real-time application of such control strategies demands high computational power that necessitates efficient digital controllers like field programmable gate array (FPGA). The inherent parallelism offered by FPGAs minimizes the execution time and exhibits an excellent cost-performance trade-off. In addition, rapid advancements in FPGA technology with a broad portfolio of intellectual property (IP) cores, design tools, and robust embedded processors resulted in a design paradigm shift. This article proposes a low-cost solution for the resource-optimized implementation of dynamic, highly accurate, and computationally intensive finite state-predictive direct current control (FS-PDCC). The challenges for implementing complex control algorithms for power converters are discussed in detail, and the control is implemented in Intel’s low-cost non-volatile FPGA-MAX^®10. An efficient design methodology using finite state machine (FSM) is adopted to achieve time/resource-efficient implementation. The parallel and pipelined architecture of FPGA provides better resource utilization with high execution speed. The experimental results prove the efficiency of FPGA-based cost-effective solutions that offer superior performance with better output quality.

The traditional Fixed Band Hysteresis Current Control (FB-HCC) though being widely used for the current control of grid integrated voltage source inverter (GI-VSI), has the drawback of variable switching frequency. To overcome this drawback, Complex Programmable Logic Device (CPLD) based switching scheme is proposed in this paper. The proposed method calls for a single reference wave and the control concept is to terminate the rising and falling inductor current ($i_L$) either by the comparator or by the CPLD, based on the nature of its slope. Termination of the $i_L$ with steeper slope by the comparator ensures lower current ripple, whereas the CPLD ensures constant switching frequency ($f_{sw}$). However, the $i_L$ obtained with the proposed logic has a DC offset, which is corrected by modifying the reference. The basic concept, switching logic, and reference correction are thoroughly detailed. MATLAB/Simulink results are included to verify the proposed concept. The constant frequency operation of the proposed method is also validated in a 2 kW, 230 V, 50 Hz GI-VSI prototype.

This paper discusses a simple and efficient rapid prototyping methodfor the field programmable gate array (FPGA) implementationof computationally intensive finite state-predictive direct currentcontrol (FS-PDCC).