The physics and performance of various advanced semiconductor devices, which are the most promising for the end of the ITRS roadmap, are investigated in a wide temperature range down to 20 K. The transport parameters in front and/or back channels in fully depleted ultrathin film SOI devices, Trigate, FinFET, Omega-gate nanowire FET and 3D-stacked SiGe nanowire FETs, fabricated with high- k dielectrics/metal gate, elevated source/drain, different channel orientations, shapes and strains, are addressed. The impacts of the gate length, Si film and wire diameter down to 10 nm, are also shown. The variations of the phonon, Coulomb, neutral defects and surface roughness scattering as a function of temperature and device architecture are highlighted. An overview of the influence of temperature on other main electrical parameters of MOSFETs, nanowires FETs and tunnel FETs, such as threshold voltage, subthreshold swing, leakage and driving currents is also given.

This paper is dedicated to a review of the international effort to map the future of nanoelectronics from materials to systems for the new electronics industry. The following sections are highlighted: the Roadmap structure with the international teams, the methodology and historical evolution, the various eras of scaling, the new ecosystems and computer industry, the evolving supply chain, the development of SoC and SiP, the advent of the Internet of Everything and the 5G communications, the dramatic increase of data centers, the power challenge, the technology fusion, heterogeneous and system integration, the emerging technologies, devices and computing architectures, and the main challenges for future applications.

A theoretical analysis of the carrier mobility in organic transistors is presented. We noticed that the assumption of zero potential at open/quasi-free surface may cause a large deviation of the areal charge density in the organic film, greater in thinner-film transistors. Taking into account this effect, the effective mobility is obtained using the Kubo–Greenwood integral, which provides the total conductivity in the band and thus in the whole organic film. The mobility is studied with respect to gate voltage and temperature, for various disorder and transport diffusivity levels, enabling a better insight of the carrier mobility in organic transistors.

The impact of the quasi-Fermi potential gradient on transconductance enhancement at low temperatures is studied for silicon NMOSFETs. Using experimental measurements and two-dimensional numerical simulations, it is shown that the influence of this gradient on transconductance becomes significant in the deep submicrometre range. This effect is explained in terms of reduction of the intrinsic channel length and moving of the Fermi level closer to the band edge at low temperatures.

We present an overview of the performances of FDSOI CMOS transistors down to deep cryogenic temperature, highlighting in particular the benefits brought by the back bias. FDSOI transistors are operational from room temperature down to temperature as low as 100mK. The main DC electrical characteristics, as well as variability properties and reliability are measured and analyzed. We also point out specific behaviors appearing at cryogenic temperature, and discuss their physical origin and modeling.

This work presents a new FET architecture which allows maximizing the electrostatic control of the transistor, equivalent to 6 or 8 gates. The GAIA (gate-all-inside-and-around) MOSFETs have enhanced flexibility, with significantly higher effective channel width for a given footprint or a footprint reduction for a given effective width, as well as better drive current and control of short channel effects compared with GAA (gate-all-around) or FinFET devices with the same footprint. Additional parameters compared with GAA and FinFET, due to the inner gate, also enable optimizing the electrical properties of GAIA MOSFETs for low power or high performance applications.