This paper details the design of a new high-speed point multiplier for elliptic curve cryptography using either field-programmable gate array or application-specified integrated circuit technology. Different levels of digit-serial computation were applied to the data path of Galois field (GF) multiplication and division to explore the resulting performances and find out an optimal digit size. We provide results for the five National Institute of Standards and Technology recommended curves, outperforming the previous published results. In GF (2 ¹⁶³ ), we achieve a point multiplication in 19.38 μs in Xilinx Virtex-E. Using the modern Xilinx Virtex-5, the point multiplication times in GF (2 m ) for m = 163, 233, 409, and 571 are 5.5, 17.8, 33.6, 102.6, 384μs, respectively, which are the fastest figures reported to date.

Modular exponentiation with large modulus and exponent, which is usually accomplished by repeated modular multiplications, has been widely used in public key cryptosystems. Typically, the Montgomery's modular-multiplication algorithm is used since no trial division is necessary, and the carry-save addition (CSA) is employed to reduce the critical path. In this paper, we optimize the Montgomery's multiplication and propose architectures to perform the least significant bit first and the most significant bit first algorithms. The developed architecture has the following distinctive characteristics: 1) use of digit serial approach for Montgomery multiplication. 2) Conversion of the CSA representation of intermediate multiplication using carry-skip addition. This allows the critical path to be reduced, albeit with a small-area speed penalty; and 3) precompute the quotient value in Montgomery's iteration in order to speed up the operating frequency. In this paper, we present results in Xilinx Virtex 5 and in 0.18-μm application-specified integrated circuit technologies. For fair comparison with previous works, Xilinx Virtex 2 results are reported. Experimental results show that the proposed modular exponentiation and modular-multiplication design obtain the best delay performance compared with the published works and outperform them in terms of area-time complexity as well.

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A new high speed machining experiment is designed to obtain orthogonal cutting in a wide range of cutting speeds from 7 m/s to 100 m/s. Quasi-stationary cutting conditions are obtained. The measurement of the longitudinal cutting force reveals the existence of an optimal cutting speed for which the energy consumption is minimum. The genuine tool-workpiece material interaction can be analyzed with that experimental device.

This paper presents a novel class of division algorithm that reduces the delay of calculus introducing more concurrency in computation. The algorithm is suitable for fixed-point operands and divides in a radix r = 2^k, producing k bits at each iteration. The proposed digit recurrence algorithm has two different architectures, a first one for general hardware implementation, and the second one optimized for configurable logic. Results show a speedup greater to three times respect to a classical non-restoring division implemented in Xilinx Devices. The dividers were also compared against Xilinx CoreGenerator circuits clearly outperforming latency and area.