FPGA-based embedded image processing systems offer considerable computing resources but present programming challenges when compared to software systems. The paper describes an approach based on an FPGA-based soft processor called Image Processing Processor (IPPro) which can operate up to 337 MHz on a high-end Xilinx FPGA family and gives details of the dataflow-based programming environment. The approach is demonstrated for a k-means clustering operation and a traffic sign recognition application, both of which have been prototyped on an Avnet Zedboard that has Xilinx Zynq-7000 system-on-chip (SoC). A number of parallel dataflow mapping options were explored giving a speed-up of 8 times for the k-means clustering using 16 IPPro cores, and a speed-up of 9.6 times for the morphology filter operation of the traffic sign recognition using 16 IPPro cores compared to their equivalent ARM-based software implementations. We show that for k-means clustering, the 16 IPPro cores implementation is 57, 28 and 1.7 times more power efficient (fps/W) than ARM Cortex-A7 CPU, nVIDIA GeForce GTX980 GPU and ARM Mali-T628 embedded GPU respectively.

Background and Objective: Falls pose a significant risk to public health, especially for the elderly population, and could potentially result in severe injuries or even death. A reliable fall detection system is urgently needed to recognise and promptly alert to falls effectively. A vision-based fall detection system has the advantage of being non-invasive and affordable compared with another popular approach using wearable sensors. Nevertheless, the present challenge lies in the algorithm's limited on-device operating speed due to extremely high computational demands, and the high computational demands are usually essential to improve the performance for the complex scene. Therefore, it is crucial to address the above challenge in computational power and complex scenes. Methods: This article presents the implementation of a real-time fall detection algorithm with low computational costs using a single webcam. The suggested method optimises precision and efficiency by synthesising the strengths of background subtraction and the human pose estimation model BlazePose. The biomechanical features, derived from body key points identified by BlazePose, are utilised in a random forest model for classifying fall events. Results: The proposed algorithm achieves 89.99% accuracy and 29.7 FPS with a laptop CPU on the UR Fall Detection dataset and the Le2i Fall Detection dataset. The algorithm shows great generalisation and robustness in different scenarios. Conclusion: Due to the low computational power of the system, the findings also suggest the potential for implementing the system in small-scale medical monitoring equipment, which maximises its practical value in digital health.

Artificial Intelligence (AI) has almost become the default approach in a wide range of applications, such as computer vision, chatbots, and natural language processing. These AI-based applications require computing large-scale data with sufficient precision, typically in floating-point numbers, within a limited time window. A primary target for AI acceleration is matrix multiplication, mainly involving dot products through Multiply-Accumulate (MAC) operations. Current research employs the Fused Multiply-Add (FMA) operation, based on IEEE-754 Floating Point (FP) standard, to meet these requirements. However, current research focuses more on simplifying the internal digital circuits of the Processing Elements (PEs) performing FMA operations, rather than optimizing the FMA process specifically for MAC tasks. Current PE arrays often use a two-dimensional (2-D) systolic array design, without specific optimization for MAC operations, thus their parallelism is not fully utilized. Additionally, these designs lack reconfigurability and flexibility, leading to suboptimal performance on Field-Programmable Gate Arrays (FPGAs). Moreover, some designs adopt lower precision computing in AI inference for higher performance. However, some AI models still rely on high-precision computing to maintain the accuracy. Thus, multi-precision computing is commonly used in AI accelerators. To address these challenges, this paper proposes a novel Multi-Fused Multiply-Accumulate (MFMA) scheme and a corresponding three-dimensional (3-D) scalable systolic FP computing architecture. The MFMA scheme addresses the problem of the classical FMA scheme. It optimizes FMA for MAC operations with the Fused Multiply-Accumulate (FMAC) operation. Also, it combines multi-precision and mixed-precision FP computing methods for higher accuracy and lower overflow error. The proposed architecture integrates two 2-D systolic arrays into the PE for a 3-D systolic array, achieving higher parallelism and flexibility. The proposed scalable architecture can be customized to suit various FMAC operations. Compared with existing state-of-the-art FP architectures on FPGAs, our proposed architecture achieves 47%, 10%, and 159% energy efficiency improvements in FP32, FP16, and INT8 operations, respectively. Furthermore, our proposed architecture achieves energy efficiency improvements of 105%, 54%, and 262% under efficiency saturation conditions, outperforming the existing state-of-the-art design.

OpenAI's ChatGPT (GPT‐4) ushers in a superior mode of computer interaction through natural language dialogues. Notably, it generates not only engaging dialogues but also codes aligned to queries and requirements. The potential of ChatGPT in hardware implementation via natural language is implemented and a strategy for “asking the right questions” is outlined. The versatility of ChatGPT is demonstrated through three mainstream hardware designs – systolic array, ResNet and MobileNet accelerators – comparing these with hand‐coded designs. The evaluation metrics include design quality, design efforts, and limitations of code generated by ChatGPT/GPT‐4/Cursor against prevalent High‐Level Synthesis or hand‐coded HDL designs. Consequently, a novel design workflow is proposed and the constraints of using GPT, particularly in AI accelerators, are highlighted.

Abstract—Automatic Modulation Classification (AMC) is a technique used to identify signal modulations in applications like IoT devices, cognitive radar, software-defined radio, and electronic warfare. These applications could be applied to IoT devices. With future wide applications of IoT devices, AMC algorithms need to be more compact yet suitable for embedded devices with limited resources and remain acceptable accuracy. Although current AMC algorithms deliver high accuracy, they require substantial computing power, making them unsuitable for IoT devices. This paper introduces the novel Chessboard-based Automatic Modulation Classification (CAMC) algorithm, which has dramatically high accuracy. Test results reveal that CAMC achieves 99%* accuracy under a 3dB SNR condition and 100% above 5dB SNR. Meanwhile, this algorithm is scalable and demands less computing power. It offers better accuracy results compared to state-of-the-art AMC algorithms, classifying mainstream modulations in IoT devices like BPSK, QPSK, 8PSK, and 16QAM, but requires less computing power than existing algorithms. Additionally, CAMC is hardware-friendly due to its inherent parallelism and scalability.