For the first time, two-layer stacked nanowire gate-all-around (GAA) negative capacitance (NC) field-effect transistors (FETs) with an ultrasmall poly-Si channel that has a size of 5.3 × 9 nm2 and a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) are experimentally demonstrated. FETs exhibit a remarkable Ion–Ioff ratio of more than 108. We demonstrated stacked channels, double layers, GAA NC-FET with a threshold voltage (VTH) of 0.61 V, and a superior subthreshold behavior with an average and minimum sub-VTH slope of 43.85 and 26.84 mV/dec, respectively. By using additional stacked channels, the density of the on-state current can be enhanced with the same channel footprint. An additional ZrO2 seed layer was inserted under the Hf1-xZrxO2 layer to improve ferroelectric crystallinity. Thus, the conventional crystallization annealing step can be omitted due to the presence of the orthorhombic phase (o-phase) before further post-metal annealing (PMA). Thus, high-performance GAA devices can be achieved through a combination of stacked channels, GAA NC-FET, and free of crystallization annealing step.

We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7×12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs exhibit low supply gate voltage (3 V), steep subthreshold swing ~99 mV/dec, and high I_ON/I_OFF >; 10⁷ (V_D = 1 V) without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D structure, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications.

In this paper, the Pi-gate (PG) poly-Si junction-less (JL) and inversion mode (IM) FETs with a high aspect ratio (A.R. = channel thickness/channel width ~ 3.4) have been successfully fabricated and demonstrated by a method without using the costly lithography technique. This method has some advantages: 1) the thickness of channels can be controlled simply by thickness of poly-Si layer; 2) the shape of channels can be controlled effectively by rectangular silicon nitride (Si ₃ N ₄ ) as hard masks; 3) the series resistance can be reduced by raised source/drain configurations; and 4) Si-compatible low thermal budget process. The PG polySi JL FETs show excellent electrical performance in terms of low gate overdrive voltage (VG-VTH = 2 V), extremely near ideal subthreshold swing (S.S.) ~68 mV/decade, steep average subthreshold swing (A.S.S.) ~ 73 mV/decade, smaller drain induced barrier lowering ~9 mV/V, a higher ON/OFF current ratio ~ 1.1 × 10 ⁸ (VD = 1 V), and a better field-effect mobility (μFE) ~ 35 (cm ² /Vs) as compared with PG poly-Si IM FETs. Thus, these devices are very promising for future 3-D integrated circuits applications.

In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing ~75 mV/decade, low drain-induced barrier lowering ~33 mV/V, and high on/off currents ratio ( $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}) \sim 7 \times 10^{6}$ can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.

The integration of 4 nm thick amorphous indium tungsten oxide (a-IWO) and a hafnium oxide (HfO₂) high-κ gate dielectric has been demonstrated previously as one of promising amorphous oxide semiconductor (AOS) thin-film transistors (TFTs). In this study, the more positive threshold voltage shift (∆V_TH) and reduced I_ON were observed when increasing the oxygen ratio during a-IWO deposition. Through simple material measurements and Technology Computer Aided Design (TCAD) analysis, the distinct correlation between different chemical species and the corresponding bulk and interface density of states (DOS) parameters were systematically deduced, validating the proposed physical mechanisms with a quantum model for a-IWO nanosheet TFT. The effects of oxygen flow on oxygen interstitial (O_i) defects were numerically proved for modulating bulk dopant concentration N_d and interface density of Gaussian acceptor trap N_GA at the front channel, significantly dominating the transfer characteristics of a-IWO TFT. Furthermore, based on the studies of density functional theory (DFT) for the correlation between formation energy E^f of O_i defect and Fermi level (E_F) position, we propose a numerical methodology for monitoring the possible concentration distribution of O_i as a function of a bias condition for AOS TFTs.