The buffer and surface trapping effects on low-frequency (LF) Y-parameters of Fe-doped AlGaN/GaN high-electron mobility transistors (HEMTs) are analyzed through experimental and simulation studies. The drain current transient (DCT) characterization is also carried out to complement the trapping investigation. The Y₂₂ and DCT measurements reveal the presence of an electron trap at 0.45–0.5 eV in the HEMT structure. On the other hand, two electron trap states at 0.2 eV and 0.45 eV are identified from the LF Y₂₁ dispersion properties of the same device. The Y-parameter simulations are performed in Sentaurus TCAD in order to detect the spatial location of the traps. As an effective approach, physics-based TCAD models are calibrated by matching the simulated I-V with the measured DC data. The effect of surface donor energy level and trap density on the two-dimensional electron gas (2DEG) density is examined. The validated Y₂₁ simulation results indicate the existence of both acceptor-like traps at E_C –0.45 eV in the GaN buffer and surface donor states at E_C –0.2 eV in the GaN/nitride interface. Thus, it is shown that LF Y₂₁ characteristics could help in differentiating the defects present in the buffer and surface region, while the DCT and Y₂₂ are mostly sensitive to the buffer traps.

The thermal resistance ( ${R}_{\text {TH}}$ ) of 0.15- and 0.25- $\mu $ m AlGaN/GaN high-electron mobility transistor (HEMT) is computed from the linear portion of simulated change in channel temperature ( $\Delta {T}$ ) versus power dissipation ( ${P}_{D}$ ) plot. The simulated I–V characteristics are validated with measured data using the Sentaurus thermodynamic TCAD model. Subsequently, ${R}_{\text {TH}}$ is estimated for the HEMT with and without a gate field-plate (FP) structure. Three linear ${R}_{\text {TH}}$ regions are observed for HEMT with FP, due to the variation in the hotspot position with the increasing drain voltage, whereas a single ${R}_{\text {TH}}$ is identified for the HEMT without FP, as the hotspot remains at the drain side of the gate edge over a wide range of dissipated power. ${R}_{\text {TH}}$ is also reported for the HEMT with different FP lengths ( ${L}_{\text {FP}}$ ), showing that ${R}_{\text {TH}}$ decreases as ${L}_{\text {FP}}$ increases. ${R}_{\text {TH}}$ is found to decrease with the gate width, which is consistent with the theory as well as the thermoreflectance and pulsed I– V measurements. A slight increase in ${R}_{\text {TH}}$ is observed upon reducing the gate voltage. Furthermore, the change in ${R}_{\text {TH}}$ is evaluated by placing thermal contact at three different locations (substrate bottom, buffer and substrate sidewall, and contacts) in the simulation. Similar observations are detected for 0.25- $\mu $ m AlGaN/GaN HEMTs.

We derived a simplified analytical expression to estimate the dynamic reduction in the 2DEG density due to the buffer trapping ( ${n}_{T}$ ) in GaN-based high-electron-mobility transistors (HEMTs). To compute ${n}_{T}$ , gate-lag drain current transient (DCT) measurements are carried out at a fixed temperature for different ${V}_{GS}$ points. The dynamic decrease in the 2DEG due to the Fe-related trap at ${E}_{C}$ -0.5 eV is found to be ~ $3.4\times10$ ¹¹ cm ⁻² in AlGaN/GaN HEMT; thus, ${n}_{T}$ is an essential quantity to evaluate the current collapse effects in HEMT. The validity of the expression is further demonstrated in the C-doped HEMTs. The calculated ${n}_{T}$ for the trap at ${E}_{C}$ -0.14 eV is about $9\times10$ ¹² cm ⁻⁰ in InAlN/GaN HEMT with C-doped buffer, and the calculated ${n}_{T}$ for the trap at ${E}_{C}$ -0.33 eV is ~ $1.2\times10$ ¹³ cm ⁻² in AlN/GaN HEMT with C-doped buffer. These values reveal that current collapse effects are more pronounced in the C-doped HEMTs than the Fe-doped HEMTs. Thus, this work is an important first step before further improvements in the model for computing buffer trap concentration.

Carrier emission rate accelerates from a trap with the increase in drain voltage due to the self-heating (SH) and Poole–Frenkel (PF) emission effects; thus, the conventional Arrhenius analysis underestimates the trap activation energy. For this purpose, this work estimates the zero-field (actual) activation energy of a trap in InAlN/GaN and AlN/GaN high-electron mobility transistors (HEMTs) by including SH and PF effects in the emission rate equation. The HEMT thermal resistance ( $\textit{R}_{\text{TH}}$ ) is computed from the technology computer aided design (TCAD) simulation results. Subsequently, the SH-induced increase in the channel temperature ( ${\sf\Delta}\textit{T}$ ) is incorporated in the Arrhenius plot, constructed from drain current transient (DCT) and output-admittance ( $\textit{Y}_{\text{22}}$ ) parameters. The apparent trap activation energy ( $\textit{E}_{\text{ap}}$ ) is calculated from the measured DCT and $\textit{Y}_{\text{22}}$ at different drain voltages, and the respective electric field ( F ) at each bias condition is extracted from the simulation. Finally, zero-field activation energy ( $\textit{E}_{\text{0}}$ ) is estimated from the $\textit{E}_{\text{ap}}$ versus ( F ) $^{\text{0.5}}$ plot intercept. $\textit{E}_{\text{0}}$ for the well-known Fe-related buffer trap is identified at $\textit{E}_{\textit{C}}- \text{0.7}$ eV in the InAlN/GaN HEMT. Similarly, $\textit{E}_{\text{0}}$ at $\textit{E}_{\textit{C}}- \text{0.51}$ eV is found for the trap in the C-doped AlN/GaN HEMT.

This paper described a comparison between a numerical Finite Element Analysis (FEA) and an analytical approach in order to extract the thermal time constants and the thermal resistances of simple but realistic structures. Understanding the complex contribution of multidimensional thermal spreading, the effect of multiple layers, and the correlation with the heat source length is mandatory due to the severe mismatch of thermal expansion in different epitaxial layers and high operating temperatures. This is especially true on GaN HEMT (High Electron Mobility Transistor) with the continuous decrease of the gate length and the increase of the power density. Moreover, in this paper, we extracted the time constants with a Model Order Reduction (MOR) technique based on the Ritz vector approach with inputs coming from the FE matrices. It was found that the time constants obtained by an analytical solution and a model order extraction from FEA were exactly the same. This result validated the idea that our MOR technique provides the real time constants and resistances for our device structures and in this case unified the analytical world with the numerical one.

Channel temperature has a strong impact on the performance of a microwave power transistor. In this paper, various methods, including electrical measurements, optical analysis, and FEM simulations, were employed to perform both transient and steady-state thermal characterization of GH15 2 × 150 µm transistors from UMS foundry (United Monolithic Semiconductors, France). The transient study allowed for the extraction of thermal time constants according to which the temperature in the transistor changes. The steady-state study provided the hotspot temperature. As the channel is physically inaccessible, direct thermal measurement at the hotspot is not possible, in order to extract the temperature of this hotspot, different measurement methods are combined by simulation, which is calibrated based on the measurements, resulting in a well-adjusted thermal model. This calibrated model enabled the extraction of temperature at any location within the device’s structure, particularly at the hotspot. The measurement and simulation results have shown that the hotspot temperature can be 30% higher than the temperature of the nearest external surface for high dissipated power levels.