Rapid growth of sensors and the Internet of Things is transforming society, the economy and the quality of life. Many devices at the extreme edge collect and transmit sensitive information wirelessly for remote computing. The device behavior can be monitored through side-channel emissions, including power consumption and electromagnetic (EM) emissions. This study presents a holistic self-testing approach incorporating nanoscale EM sensing devices and an energy-efficient learning module to detect security threats and malicious attacks directly at the front-end sensors. The built-in threat detection approach using the intelligent EM sensors distributed on the power lines is developed to detect abnormal data activities without degrading the performance while achieving good energy efficiency. The minimal usage of energy and space can allow the energy-constrained wireless devices to have an on-chip detection system to predict malicious attacks rapidly in the front line.

With the advent of globalization, hardware trojans provide an ever-present threat to the security of devices. Much of the research to date has centered around documenting and providing detection methods for digital trojans. Few, however, have explored the space of trojans in the RF/analog front end. Two hardware trojans, an analytical analysis of the trojan impacts on two different types of amplifiers, and an unsupervised ML detection method for edge IOT applications using magnetic tunnel junction sensors for side-channel monitoring are explored. A classification autoencoder for anomaly detection is presented with an accuracy of greater than 90% with both single tone and BLE data is presented.

This work presents a fully unrolled on-chip deep reinforcement learning (DRL) module with a deep Q-network (DQN) and its system integration for integrated circuits control and functionality augmentation tasks, including voltage regulation of a cryogenic single-input triple-output DC-DC converter and recovery of RF fingerprints (RFFs) using a reconfigurable power amplifier (PA) under temperature variations. The complete DRL module features 6-bit fixed-point model parameters, 116 KB of memory, and 128 processing elements. It is equipped with on-chip training capabilities, fully unrolled on a 0.45 mm2 core area using 28 nm technology. The design achieves an efficiency of 0.12 nJ per action and a control latency of 4.925 ls, with a maximum operational efficiency of 3.49 TOPS/W. Temperature effects on the chip are thoroughly demonstrated across a wide temperature range from 358 K (85 0C) to 4.2 K (–269 0C).