A frequency tunable phase-locked loop (PLL) applied in high energy particle detector has been developed. In order to achieve high detection efficiency, high requirements are promoted for on-chip clock in CMOS pixel sensors, which requires high precision and low power consumption for the PLL. The proposed PLL employs a fractional-N frequency division structure. An LC voltage-controlled oscillator (LC-VCO) is used to generate the local clock. A third-order MASH sigma-delta (Σ - Δ) modulator is used to alleviate the quantization noise introduced by the fractional-N frequency divider. In order to further reduce the phase noise, pre-set and post-set binary frequency dividers are employed. In the prototype chip a low dropout regulator (LDO) is integrated to suppress the power supply noise. The PLL was designed and fabricated in a 180 nm CMOS process. It costs an area of 1.29 mm ² and a power of 8.1 mW at a 1.8 V power supply. The measured output frequency range is 400 - 530 MHz with the reference frequency of 25 - 35 MHz. The RMS jitter, integrated from 100 kHz to 100 MHz, is 4.8 ps at 526 MHz. The in-band spur is less than -61 dBc, and the phase noise at 1 MHz frequency offset is less than -113 dBc/Hz.

The Circular Electron Positron Collider (CEPC) has been proposed to enable more thorough and precise measurements of the properties of Higgs, W, and Z bosons, as well as to search for new physics. In response to the stringent performance requirements of the vertex detector for the CEPC, a baseline vertex detector prototype was tested and characterized for the first time using a 6GeV electron beam at DESY II Test Beam Line 21. The baseline vertex detector prototype is designed with a cylindrical barrel structure that contains six double-sided detector modules (ladders). Each side of the ladder includes TaichuPix-3 sensors based on Monolithic Active Pixel Sensor (MAPS) technology, a flexible printed circuit, and a carbon fiber support structure. Additionally, the readout electronics and the Data Acquisition system were also examined during this beam test. The performance of the prototype was evaluated using an electron beam that passed through six ladders in a perpendicular direction. The offline data analysis indicates a spatial resolution of about 5 μm, with detection efficiency exceeding 99% and an impact parameter resolution of about 5.1 μm. These promising results from this baseline vertex detector prototype mark a significant step toward realizing the optimal vertex detector for the CEPC.

Industrial engineering design is a crucial issue in manufacturing. To meet the competitive global market, manufacturers are continuously seeking solutions to design industrial products and systems inventively. Su-Field analysis, which is one of the TRIZ analysis tools for inventive design problems, has been used to effectively improve the performance of industrial systems. However, the inventive standards used for engineering design are summarized and classified according to a large number of patents in different fields. They are built on a highly abstract basis and are independent of specific application fields, making their use require much more technical knowledge than other TRIZ tools. To facilitate the use of invention standards, in particular to capture the uncertainty or imprecision described in the standards, this paper proposes a rule-based heuristic approach. First, Su-Field analysis ontology and fuzzy analysis ontology are constructed to represent precise and fuzzy knowledge in the process of solving inventive problems respectively. Then, SWRL (Semantic Web Rule Language) reasoning and fuzzy reasoning are executed to generate heuristic conceptual solutions. Finally, we develop a software prototype and elaborate the resolution of “Auguste Piccard’s Stratostat ” in the prototype.

The Circular Electron Positron Collider (CEPC) proposed by the Chinese high energy physics community is aiming to measure Higgs particles and their interactions precisely. The tracking detector including Silicon Inner Tracker (SIT) and Forward Tracking Disks (FTD) has driven stringent requirements on sensor technologies in term of spatial resolution, power consumption and readout speed. CMOS Pixel Sensor (CPS) is a promising candidate to approach these requirements. This paper presents the preliminary studies on the sensor optimization for tracking detector to achieve high collection efficiency while keeping necessary spatial resolution. Detailed studies have been performed on the charge collection using a 0.18 μm CMOS image sensor process. This process allows high resistivity epitaxial layer, leading to a significant improvement on the charge collection and therefore improving the radiation tolerance. Together with the simulation results, the first exploratory prototype has bee designed and fabricated. The prototype includes 9 different pixel arrays, which vary in terms of pixel pitch, diode size and geometry. The total area of the prototype amounts to 2 × 7.88 mm².