Embedding Artificial Intelligence onto low-power devices is a challenging task that has been partly overcome with recent advances in machine learning and hardware design. Presently, deep neural networks can be deployed on embedded targets to perform different tasks such as speech recognition, object detection or Human Activity Recognition. However, there is still room for optimization of deep neural networks onto embedded devices. These optimizations mainly address power consumption, memory and real-time constraints, but also an easier deployment at the edge. Moreover, there is still a need for a better understanding of what can be achieved for different use cases. This work focuses on quantization and deployment of deep neural networks onto low-power 32-bit microcontrollers. The quantization methods, relevant in the context of an embedded execution onto a microcontroller, are first outlined. Then, a new framework for end-to-end deep neural networks training, quantization and deployment is presented. This framework, called MicroAI, is designed as an alternative to existing inference engines (TensorFlow Lite for Microcontrollers and STM32Cube.AI). Our framework can indeed be easily adjusted and/or extended for specific use cases. Execution using single precision 32-bit floating-point as well as fixed-point on 8- and 16 bits integers are supported. The proposed quantization method is evaluated with three different datasets (UCI-HAR, Spoken MNIST and GTSRB). Finally, a comparison study between MicroAI and both existing embedded inference engines is provided in terms of memory and power efficiency. On-device evaluation is done using ARM Cortex-M4F-based microcontrollers (Ambiq Apollo3 and STM32L452RE).

Human activity recognition can help in elderly care by monitoring the physical activities of a subject and identifying a degradation in physical abilities. Vision-based approaches require setting up cameras in the environment, while most body-worn sensor approaches can be a burden on the elderly due to the need of wearing additional devices. Another solution consists in using smart glasses, a much less intrusive device that also leverages the fact that the elderly often already wear glasses. In this article, we propose UCA-EHAR, a novel dataset for human activity recognition using smart glasses. UCA-EHAR addresses the lack of usable data from smart glasses for human activity recognition purpose. The data are collected from a gyroscope, an accelerometer and a barometer embedded onto smart glasses with 20 subjects performing 8 different activities (STANDING, SITTING, WALKING, LYING, WALKING_DOWNSTAIRS, WALKING_UPSTAIRS, RUNNING, and DRINKING). Results of the classification task are provided using a residual neural network. Additionally, the neural network is quantized and deployed on the smart glasses using the open-source MicroAI framework in order to provide a live human activity recognition application based on our dataset. Power consumption is also analysed when performing live inference on the smart glasses’ microcontroller.

While Spiking Neural Networks (SNNs) offer a promising path toward energy-efficient edge intelligence, conventional Binary representations often suffer from high inference latency and discretization errors. Multi-level (graded) spike models address these limitations by increasing information density per pulse, yet they typically necessitate power-hungry Multiply-Accumulate units that nullify the energy advantages of neuromorphic hardware. In this work, we propose a hardware-algorithm co-design framework that leverages multi-level Integrate-and-Fire neurons coupled with a specialized multiplier-less architecture. By decomposing multi-level interactions into a cascaded shift-and-add logic, our hardware preserves the event-driven sparsity of SNNs while supporting high-precision activations. We evaluate our proposed accelerator on the Xilinx Zynq MPSoC ZCU102 platform using the Google Speech Commands (GSCs), CIFAR-10, and DVS-Gesture datasets. Experimental results demonstrate that the graded spike paradigm achieves up to a 6.7 × reduction in total spike activity through temporal information compression. Compared with the binary baseline benchmark on the DVS Gesture dataset, the proposed architecture reduces memory accesses by 68.59%, improves steady-state throughput from 33.08 FPS to 251 FPS, and increases energy efficiency from 9.01 to 54.96 GOPS W − 1 . Furthermore, by minimizing pipeline stalls and workload imbalance, our design achieves an Efficiency-per-Processing-Element of up to 3.05 GOPS W − 1 PE − 1 , thereby providing a competitive PE-level energy efficiency compared with representative SNN accelerators. This research provides a scalable pathway for deploying high-performance, ‘always-on’ neuromorphic systems in resource-constrained environments.