Mathieu Léonardon

Dr. Mathieu Léonardon

IMT Atlantique, Brest, Bretagne, France
orcid

Research Focus & Metrics

Academic Career Length

8Years (2019-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 July 2019 in SoftwareX
Verified
Journal Article
Open access
ACAdrien Cassagne
Adrien Cassagne
OHOlivier Hartmann
Olivier Hartmann
MLMathieu Léonardon
Mathieu Léonardon
KHKun He
Kun He
CLCamille Leroux
Camille Leroux
CJChristophe Jégo
Christophe Jégo

4 March 2022 in Journal of Imaging
Verified
Journal Article
Open access
PDF file
HTHugo Tessier
Hugo Tessier
VGVincent Gripon
Vincent Gripon
MLMathieu Léonardon
Mathieu Léonardon
MAMatthieu Arzel
Matthieu Arzel
THThomas Hannagan
Thomas Hannagan
DBDavid Bertrand
David Bertrand
Introduced in the late 1980s for generalization purposes, pruning has now become a staple for compressing deep neural networks. Despite many innovations in recent decades, pruning approaches still face core issues that hinder their performance or scalability. Drawing inspiration from early work in the field, and especially the use of weight decay to achieve sparsity, we introduce Selective Weight Decay (SWD), which carries out efficient, continuous pruning throughout training. Our approach, theoretically grounded on Lagrangian smoothing, is versatile and can be applied to multiple tasks, networks, and pruning structures. We show that SWD compares favorably to state-of-the-art approaches, in terms of performance-to-parameters ratio, on the CIFAR-10, Cora, and ImageNet ILSVRC2012 datasets.

18 January 2019 in Journal of Signal Processing Systems
Verified
Journal Article
Closed access
PDF file
MLMathieu Léonardon
Mathieu Léonardon
ACAdrien Cassagne
Adrien Cassagne
CLCamille Leroux
Camille Leroux
CJChristophe Jégo
Christophe Jégo
LHLouis-Philippe Hamelin
Louis-Philippe Hamelin
YSYvon Savaria
Yvon Savaria

9 January 2019 in IEEE Access
Verified
Journal Article
Open access
AGAlireza Ghaffari
Alireza Ghaffari
MLMathieu Léonardon
Mathieu Léonardon
ACAdrien Cassagne
Adrien Cassagne
CLCamille Leroux
Camille Leroux
YSYvon Savaria
Yvon Savaria

9 May 2022 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verified
Journal Article
Closed access
KAkhaled Alhaj ali
khaled Alhaj ali
Amer BaghdadiAmer Baghdadi
Amer Baghdadi
EDElsa Dupraz
Elsa Dupraz
MLMathieu Léonardon
Mathieu Léonardon
Mostafa RIZKMostafa RIZK
Mostafa RIZK
JDJean-Philippe Diguet
Jean-Philippe Diguet
Convolutional neural networks (CNNs) have proven very effective in a variety of practical applications involving artificial intelligence (AI). However, the layer depth of CNN deepens as user applications become more sophisticated, resulting in a huge number of operations and increased memory size. The massive amount of the produced intermediate data leads to intensive data movement between memory and computing cores causing a real bottleneck. In-memory computing (IMC) aims to address this bottleneck by directly computing inside memory, eliminating energy-intensive and time-consuming data movement. On the other hand, the emerging binary neural networks (BNNs), which is a special case of CNN, show a number of hardware-friendly properties, including memory saving. In BNN, the costly floating-point multiply-and-accumulate is replaced with lightweight bitwise xnor and popcount operations. In this article, we propose an IMC programmable architecture targeting efficient implementation of BNN. Computational memories based on the recently introduced memristor overwrite logic (MOL) design style are employed. The architecture, which is presented in semiparallel and parallel models, efficiently executes the advanced quantization algorithm of xnor-Net BNN. Performance evaluation based on the CIFAR-10 dataset demonstrates between 1.24x and 3x speedup and 49% and 99% energy saving compared to state-of-the-art implementations and up to 273-image/s/W throughput efficiency.