In this study, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance and are grouped into 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to system-on-chips (especially for advanced nodes) will be discussed. Different substrates such as size, pin-count, and metal line width and spacing for advanced packaging are examined. The lateral communication between chiplets such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound as well as flexible bridges will be presented. Fan-in packaging such as the six-side molded wafer-level chip scale package (WLCSP) and its comparison with the ordinary WLCSP are presented. Fan-out packaging such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference will be provided. Low loss dielectric materials for high-speed and high-frequency applications in advanced packaging will be presented. Flip chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first.

In this study, the recent advances and trends in Cu-Cu hybrid bonding will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of Cu-Cu bumpless hybrid bonding. Also, some recommendations will be provided.

In this paper, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC cap, reconstituted carrier material and thickness, and die-attach film, on the warpage after postmold cure and backgrinding of the EMC. The simulation results are compared to the experimental measurements. Also, the thermal performance (junction-to-ambient thermal resistance) of FOWLP with various chip thicknesses is characterized. Finally, some FOWLP important parameters affecting the warpage and thermal performances are recommended.

The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

The design, materials, process, fabrication, and reliability of fan-out wafer-level packaging (FOWLP) with chip-first and die face-up method are investigated in this paper. Emphasis is placed on the issues and their solutions (such as reconstituted carrier, die-attach film placement, pitch compensation, die shift, epoxy molding compound dispensing, compression molding, warpage, and Cu revealing) during the fabrication of a very large test chip (10 mm × 10 mm × 150 μm) and test package (13.47 mm x 13.47 mm), and three redistribution layers with the smallest linewidth/spacing = 5 μm/5 μm. The FOWLP test package on a six-layer printed circuit board is subjected to 1000 drops of the shock test with a magnitude = 1500 G/ms. Recommendations of process integration and guidelines on FOWLP with chip-first and die face-up are provided.

In this study, chiplet design and heterogeneous integration packaging, especially (a) chip partition and heterogeneous integration driven by cost and technology optimization, Figs. 1(a) and 1(b) chip split and heterogeneous integration driven by cost and yield, Figs. 1(b) and 1(c) multiple system and heterogeneous integration with thin-film layers directly on top of a build-up package substrate, Figs. 1(c) and 1(d) multiple system and heterogeneous integration with an organic interposer on top of a build-up package substrate, Figs. 1(d) and 1(e) multiple system and heterogeneous integration with through-silicon via (TSV) interposer on top of a build-up package substrate, Fig. 1(e), will be investigated. Figures 1(c)–1(e) are driven by formfactor and performance. Emphasis is placed on their advantages and disadvantages, design, materials, process, and examples. Some recommendations will also be provided.