Optical receiver front ends that are intentionally designed to have a bandwidth low enough that significant inter-symbol interference (ISI) is introduced are becoming commonplace. Although the resultant ISI must be removed using an equalizer, the lower bandwidth allows for higher gain in the front-end's first stage, lower input-referred noise, and fewer gain stages. With fewer main-amplifier stages, power dissipation is reduced. The noise analysis of these front ends presents several challenges. This paper derives integrated input-referred noise for inverter-based shunt-feedback transimpedance amplifiers from first principles and highlights the importance of correctly estimating the gain and noise bandwidth of the receiver. The notion of the effective gain of the receiver is introduced, which is lower than the midband gain typically used in noise calculations. The analysis of the inverter-based TIA is used to discuss the important design tradeoffs depending on the type of equalizer used. Integrated input-referred noise is derived and compared for front ends using decision-feedback equalizers (DFEs), continuous-time linear equalizers, and feed-forward equalizers. The simulation results show that a DFE-based receiver achieves the lowest input-referred noise.

This paper presents a low-power, high-gain, and wide–dynamic range (DR) photoplethysmography (PPG) sensory system with a novel direct current (DC) compensation loop and light emitting diode (LED) dimming control. The proposed PPG system exhibits a signal-aware performance, where, at strong PPG signal levels, the DC compensation loop’s capability of removing DC photocurrent is increased and the LED’s driving current is reduced. This ability allows the entire DR to be utilized by the useful alternating current component of the signal and reduces power dissipation. Fabricated in 0.35 μm standard CMOS technology, the proposed PPG sensor occupies an area of 1.744 mm ² . The proposed system exhibits a high gain and a low input-referred noise current of 19.6 MΩ and 11.23 pA _rms , respectively, while dissipating only 9.9 μW of power at the receiver’s analog frontend. The proposed DC compensation loop can remove up to 80 μA of DC photocurrent for 2% total harmonic distortion, achieving a DR of 137 dB. An external microcontroller unit uses a machine learning algorithm to extract blood pressure (BP) from the analog output of the implemented PPG sensor chip. Measurements from eight human subjects show a mean absolute error and a standard deviation of 2.25±2.82 mmHg for systolic BP and 5.01±2.10 mmHg for diastolic BP.

The integration of optical receivers in nanoscale CMOS technologies is challenging due to less intrinsic gain and more noise compared to SiGe BiCMOS technologies. Recent research revealed that low-noise, high-gain, and low-power CMOS optical receivers can be designed by limiting the bandwidth of the front-end followed by equalization techniques that benefit from good switching characteristics offered by CMOS technologies. In this tutorial brief, the operation of decision-feedback equalization, feed-forward equalization, and continuous-time linear equalization is reviewed in the context of high baud-rate 2-PAM and 4-PAM modulation. Recent advances and techniques in 4-PAM optical receivers are reviewed and compared in terms of speed, sensitivity, bandwidth, and efficiency.

Recently published CMOS optical receivers consist of a limited-bandwidth first-stage transimpedance amplifier (TIA) followed by an equalizer. Limiting the TIA’s bandwidth improves the gain and reduces the noise but introduces a significant inter-symbol interference (ISI) that is dealt with by the subsequent equalizer. Continuous-time linear equalizer (CTLE) is a commonly used equalizer in both electrical and optical links. However, recent research reported different findings about CTLE-based optical receivers. Some research papers concluded that CTLEs boost high-frequency noise compared to a full-bandwidth design. Other publications reported that high-frequency noise remains unaffected while white noise is significantly reduced. This work aims to solve this discrepancy by presenting an accurate analysis for CTLE-based optical receivers considering noise, gain, and jitter. We show that the noise performance depends on the pole/zero locations of the limited-bandwidth (LBW)-TIA and the follow-on equalizer. A properly designed CTLE-based receiver achieves a 2.5 × higher gain and a 1.74× better noise than the full-bandwidth design. The CTLE is also compared to the well-known decision feedback equalizer (DFE). The noise performance of the CTLE-based receiver lies between that of finite and infinite impulse response DFE-based receivers but achieves better gain than both architectures.

In this paper, a photodiode (PD)/transimpedance (TIA) interface is presented. The cathode terminal of the PD is AC-coupled to one of the inputs of a pseudo-differential TIA while the anode terminal is DC-coupled to the other input of the TIA. The DC-coupled input provides a path for the low-frequency component of the input signal to reach the output. This component is extracted by a baseline wander compensation scheme (BWCS) and fed to the input to eliminate signal drift after long data runs. Compared with the conventional pseudo-differential receiver, the proposed interface doubles the gain and improves the gain-bandwidth product (GBW) and the signal-to-noise ratio (SNR) by 1.37× and 5.55dB, respectively, while maintaining 209× smaller low cutoff frequency than the AC coupled receiver. The proposed interface is compatible with any TIA topology. Post-layout simulations and analytical models validate the feasibility of the proposed technique.

This article explores the power-sensitivity trade-off in optical receivers aiming to improve the energy-efficiency of the overall link. Optical receivers with field-effect transistor (FET) front-ends (FEs) are usually designed for optimal noise performance by matching the circuit’s input capacitance $\left ({C_{I} }\right)$ to the total input parasitic capacitance $\left ({C_{D} }\right)$ . However, the receiver’s power dissipation is also proportional to the input capacitance $C_{I}$ . Therefore, this paper studies the feasibility of the capacitive matching rule in the context of minimizing the power dissipation of the overall link. For that purpose, design trade-offs for the receiver, transmitter, and the overall link are presented. Comparisons are made to study how much the receiver can be downsized, sacrificing optimal noise performance, before its power reduction is offset by the transmitter’s increase in power. Simulation results show that energy-efficient links require low-power receivers with input capacitance much smaller than that required for noise-optimum performance. As an example, for a 25 Gb/s operation, an optical loss budget of 12.6 dB, and a receiver designed in 65 nm CMOS technology with $C_{D}$ of 200 fF, the overall link dissipates 2.55 pJ/bit when the receiver’s noise is minimized, leading to a receiver with $C_{I}/C_{D}=1.29$ . When optimized for overall link efficiency, the receiver size is significantly reduced to $C_{I}/C_{D}=0.38$ and the link’s energy-efficiency also improves to 1.41 pJ/bit. If the link budget or knowledge of the transmitter side is incomplete, our analysis indicates that maximizing gain with value of $C_{I}/C_{D}=0.5$ is a reasonable choice.