Surachoke Thanapitak

Dr. Surachoke Thanapitak


Research Focus & Metrics

Academic Career Length

18Years (2009-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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29 August 2018 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Journal Article
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CSChutham Sawigun
Chutham Sawigun
STSurachoke Thanapitak
Surachoke Thanapitak
This paper presents a differential fourth-order low-pass filter suitable for electrocardiography (ECG) acquisition. It is formed by cascading two compact and power-efficient biquads operating in the subthreshold region. Each biquad combines two capacitors and a flipped voltage follower circuit. The filter attains a cutoff frequency adjustable to cover the entire range of ECG (150–250 Hz). The filter prototype has been fabricated in a 0.35- $\mu \text{m}$ CMOS technology. It occupies an area of $362\,\,\mu \text {m} \times 466 \,\,\mu \text{m}$ and operates from a 0.6-V supply. Measurements confirm that the filter consumes 0.9-nW static power for a 101-Hz cutoff frequency and contributes the input-referred noise of 46.27 $\mu \text{V}_{\mathbf {rms}}$ . For a 60-Hz input frequency, the filter achieves a dynamic range of 47 dB where the third-harmonic distortion of −60 dB is produced. This leads to the figure of merit of $46.5 \times 10^{-18}$ J. When the chip area is also concerned, the proposed filter performs comparably to the recent state-of-the-art nanowatt-class low-pass filter.

12 March 2018 in IEEE Transactions on Circuits and Systems I: Regular Papers
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Journal Article
Closed access
STSurachoke Thanapitak
Surachoke Thanapitak
CSChutham Sawigun
Chutham Sawigun
This paper develops a compact power-efficient CMOS buffer to operate as a nanopower lowpass biquadratic cell. Unlike other recently reported CMOS biquads with passband gains that are attenuated by the bulk effect, this biquad attains a near 0-dB passband gain without gain compensation. It acquires the same levels of input and output common-mode voltages making it useful for cascade realization of a higher order lowpass filter. To demonstrate the potential application of the proposed biquad, a fourth-order lowpass filter was designed based on the proposed biquad circuit and fabricated in the 0.35-μm CMOS process to serve electrocardiography readout systems. Measurement results show that the filter consumes 4.26-nW static power from a 0.9-V supply providing a 100-Hz cutoff frequency. The prototype chip occupies a silicon area of 0.11 mm² and contributes an input-referred noise of 80.5 μVrms. For a 60-Hz input frequency associated with -50-dB third-order harmonic distortion, a dynamic range of 48.2 dB is achieved. The lowest power supply rejection ratio of 40 dB was obtained at 100 Hz. Compared with the previous state-of-the-art designs in the category of nanopower filters, the proposed filter consumes the least power from the lowest supply voltage.

24 December 2018 in IEEE Transactions on Circuits and Systems I: Regular Papers
Verified
Journal Article
Closed access
CSChutham Sawigun
Chutham Sawigun
STSurachoke Thanapitak
Surachoke Thanapitak
A nanopower CMOS 4th-order lowpass filter suitable for biomedical applications is presented. The filter is formed by cascading two types of subthreshold current-reuse biquadratic cell. Each proposed cell is capable of neutralizing the bulk effect that induces the passband attenuation. The nearly 0-dB passband gain can thus be maintained, while the entire filter circuit remains compact and power-efficient. Designed for electrocardiogram detection as an example of application, the filter prototype has been fabricated in a 0.35 μm CMOS process occupying 269 μm x 383 μm chip area. Measurements verify that the filter can operate from a 1.5-V single supply and consumes 5.25 nW, while providing a cutoff frequency of 100 Hz and input-referred noise of 39.38 μVrms. The intermodulation-free dynamic range of 51.48 dB is obtained from a two-tone test of 50 and 60 Hz input frequencies. Compared with state-of-the-art nanopower lowpass filters using the most relevant and reasonable figure of merit, the proposed filter ranks the best.

3 June 2021 in IEEE Transactions on Biomedical Circuits and Systems
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Journal Article
Closed access
CSChutham Sawigun
Chutham Sawigun
STSurachoke Thanapitak
Surachoke Thanapitak
This paper presents a compact DDA-based fully-differential CMOS instrumentation amplifier dedicated for micro-power ECG monitoring. Only eight transistors are employed to realize a power-efficient current-sharing DDA. A RC network (using MOS pseudo resistors and poly capacitors) forms feedback loops around the DDA creating an ac-only amplification. The proposed amplifier is dc-coupled via gate terminals of the p-channel input transistors. It thus achieves sufficiently high input impedance over the entire ECG frequency range. Fabricated in a 0.35-μm CMOS process, the proposed amplifier occupies 0.0712 mm 2 . It operates from a 2 V dc supply with 336 nA current consumption. Measurements show that the amplifier attains its input impedance of 57.5 MΩ at 150 Hz and achieves 1.54 μV rms input-referred noise over 0.1-300 Hz. Noise and power efficiency factors are 2.02 and 8.16, respectively. At 50 Hz, the mean CMRR of 83.24 dB is obtained from 11-chip measurement. Experiments performed on a human subject confirm the functionality of the proposed amplifier in a real measurement scenario.

6 April 2023 in IEEE Transactions on Biomedical Circuits and Systems
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Journal Article
Closed access
STSurachoke Thanapitak
Surachoke Thanapitak
WSWanlop Surakampontorn
Wanlop Surakampontorn
CSChutham Sawigun
Chutham Sawigun
A chopper instrumentation amplifier (IA) dedicated for bio-potential acquisition usually requires a linearized input stage for large electrode offset voltage accommodation. This linearization leads to excessive power consumption when sufficiently low input-referred noise (IRN) is required. We present a current-balance IA (CBIA) without the need for the input stage linearization. It uses two transistors to operate as an input transconductance stage and a dc-servo loop (DSL) at the same time. An off-chip capacitor completes the DSL by ac coupling the source terminals of the input transistors via chopping switches realizing a sub-Hz high-pass cutoff frequency for dc rejection. Fabricated in a 0.35-μm CMOS process, the proposed CBIA occupies 0.41 mm 2 and consumes 1.19 μW from a 3 V dc supply. Measurements show that the IA achieves an input-referred noise of 0.91 μV rms over 100 Hz bandwidth. This corresponds to a noise efficiency factor of 2.22. Typical CMRR of 102.1 dB is achieved for zero offset and degraded to 85.9 dB when a ±0.3 V input offset was applied. Gain variation of 0.5% is maintained within the range of ±0.4 V input offset. The resulting performance meets well with the requirement for ECG and EEG recording using dry electrodes. A demonstration for the use of the proposed IA on a human subject is also provided.

18 July 2012 in IEEE Transactions on Biomedical Circuits and Systems
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Journal Article
Closed access
STSurachoke Thanapitak
Surachoke Thanapitak
CTChristofer Toumazou
Christofer Toumazou
Implementation of the current mode CMOS circuit for chemical synapses (AMPA and NMDA receptors) with dynamic change of glutamate as the neurotransmitter input is presented in this paper. Additionally, circuit realisation for receptor GABA A and GABA B with an electrical signal which symbolises γ -Aminobutyric Acid (GABA) perturbation is introduced. The chemical sensor for glutamate sensing is the modified ISFET with enzyme (glutamate oxidase) immobilisation. The measured results from these biomimetics chemical synapse circuits closely match with the simulation result from the mathematical model. The total power consumption of the whole chip (four chemical synapse circuits and all auxiliary circuits) is 168.3 μW. The total chip area is 3 mm 2 in 0.35-μm AMS CMOS technology.