Deep Neural Networks (DNNs) have shown significant advantages in many domains, such as pattern recognition, prediction, and control optimization. The edge computing demand in the Internet-of-Things (IoTs) era has motivated many kinds of computing platforms to accelerate DNN operations. However, due to the massive parallel processing, the performance of the current large-scale artificial neural network is often limited by the huge communication overheads and storage requirements. As a result, efficient interconnection and data movement mechanisms for future on-chip artificial intelligence (AI) accelerators are worthy of study. Currently, a large body of research aims to find an efficient on-chip interconnection to achieve low-power and high-bandwidth DNN computing. This paper provides a comprehensive investigation of the recent advances in efficient on-chip interconnection and design methodology of the DNN accelerator design. First, we provide an overview of the different interconnection methods on the DNN accelerator. Then, the interconnection methods on the non-ASIC DNN accelerator will be discussed. On the other hand, with the flexible interconnection, the DNN accelerator can support different computing flow, which increases the computing flexibility. With this motivation, reconfigurable DNN computing with flexible on-chip interconnection will be investigated in this paper. Finally, we investigate the emerging interconnection technologies (e.g., in/near-memory processing) for the DNN accelerator design. This paper systematically investigates the interconnection networks in modern DNN accelerator designs. With this article, the readers are able to: 1) understand the interconnection design for DNN accelerators; 2) evaluate DNNs with different on-chip interconnection; 3) familiarize with the trade-offs under different interconnections.

Network-on-Chip (NoC) is the regular and scalable design architecture for chip multiprocessor (CMP) systems. With the increasing number of cores and the scaling of network in deep submicron (DSM) technology, the NoC systems become subject to manufacturing defects and have low production yield. Due to the fault issues, the reduction in the number of available routing paths for packet delivery may cause severe traffic congestion and even to a system crash. Therefore, the fault-tolerant routing algorithm is desired to maintain the correctness of system functionality. To overcome fault problems, conventional fault-tolerant routing algorithms employ fault information and buffer occupancy information of the local regions. However, the information only provides a limited view of traffic in the network, which still results in heavy traffic congestion. To achieve fault-resilient packet delivery and traffic balancing, this work proposes a Path-Diversity-Aware Fault-Tolerant Routing ( PDA-FTR ) algorithm, which simultaneously considers path diversity information and buffer information. Compared with other fault-tolerant routing algorithms, the proposed work can improve average saturation throughput by 175 percent with only 8.9 percent average area overhead and 7.1 percent average power overhead.

The superiority of various Deep Neural Networks (DNN) models, such as Convolutional Neural Networks (CNN), Generative Adversarial Networks (GAN), and Recurrent Neural Networks (RNN), has been proven in various real-world applications and has received much attention. However, different DNN models include various types of operations. For example, CNN models are usually composed of convolutional layers (Conv) and fully-connected layers (FC). Furthermore, some light CNN models such as MobileNet adopt depthwise separable convolution with depthwise convolution (DWC) and pointwise convolution (PWC) to compress the models. In addition to regular convolution, de-convolution (De-Conv) is also widely used in many GAN models. Moreover, many RNN models also employ long-short-term memory (LSTM) to control update of internal states and data. Such a high diversity of various DNN operations poses great design challenges in implementing reconfigurable Deep Learning (DL) accelerators, which can support various types of DNN operations. Most recent DL accelerators focus only on some DNN operations, which lacks computing flexibility. In this paper, by exploiting the sparsity in current DNN models, we design sparsity-aware DL hardware accelerators that can support efficient computation of various DNN operations, including Conv, DeConv, DWC, PWC, FC, and LSTM. Through reconfiguring dataflow and parallelizing different operations, the proposed designs not only improve system performance but also increase hardware utilization with a significant reduction of power consumption in memory accesses and arithmetic computations.

As the complexity of the multicore system grows, the large workload diversity results in serious thermal problems. In a practical way, the number of placed thermal sensors is usually limited due to the manufacturing cost. In recent years, the compressive sensing (CS) theory is proven as an efficient way to reconstruct the original signal by using fewer sampling data. However, due to the high computational complexity during the signal reconstruction, the CS theory is not appropriate to apply to the real-time temperature monitoring in the current multicore system. In this article, we propose a grid-based sensor placement approach to placement the number-limited thermal sensors on the target multicore system. On the other hand, we adopt the matrix inversion bypass (MIB) property to reduce the computational complexity of two widely used signal reconstruction approaches in CS theory [i.e., the orthogonal matching pursuit (OMP) and stagewise OMP (StOMP)]. Due to the characteristic of random sampling in CS theory, the complexity of thermal sensor placement for multicore systems can be reduced significantly. In addition, the proposed MIB-based temperature reconstruction method helps to satisfy the requirement of real-time temperature estimation. The experimental results show that the proposed approach can reduce 57%–93% average full-system temperature reconstruction error compared with the previous non-CS-based approaches. Besides, we can also reduce 22%–41% computing latency compared with the current CS-based reconstruction algorithm. Due to the MIB-based operation, we can bypass the matrix inversion operation for temperature reconstruction. Therefore, the hardware overhead of the temperature reconstruction unit can be reduced significantly. Compared with the conventional approaches, we can reduce 24%–87% area overhead and improve 50%–220% hardware efficiency.

As the complexity of multicore system grows with respect to the technology development, the Network-on-Chip (NoC) provides flexible and scalable interconnection for the multicore systems. However, as the complexity of the network increases, the large workload diversity and the time-varying workload distribution result in large power density, which leads to severer thermal problems and makes the temperature distribution of the system become time-varying. To prevent the multicore systems from overheating, in a practical way, many thermal sensors are embedded in the system. However, due to the manufacturing cost constraints, it is not a viable option to involve a massive number of embedded thermal sensors. Therefore, searching for the appropriate locations in offline design phase to allocate the number-limited thermal sensors, which will be used to sense the time-varying system temperature behavior at runtime, is a design challenge. On the other hand, full-chip temperature distribution tracking based on the restricted temperature sensing information affects the efficiency of the involved temperature management. In this paper, we first present a novel thermal sensor allocation methodology by considering the time-varying temperature behavior on the chip according to different applications. Besides, a linear-regression-based reconstruction algorithm is proposed to estimate the full-chip temperature distribution according to the number-limited thermal sensing results. At last, a framework of temperature management with restricted temperature sensing information is introduced. Compared with the conventional methods, the proposed approach can reduce 28% to 92% average error of full-chip temperature estimation, which helps to improve the average system throughput by 60% to 70%.

Driven by the data-centric industrial revolution, Prognostics and Health Management (PHM) technology based on sophisticated Deep Learning (DL) methods has become crucial for industrial fault diagnosis. Based on well-labeled data, the DL methods further improve PHM development. However, the efficiency of the involved DL methods is impacted significantly due to the limited data collection. To address this problem, Source Free-Unsupervised Domain Adaptation (SF-UDA) has been proposed to improve DL efficiency without fully labeled source data. However, the traditional SF-UDA methods are constrained by predefined label numbers and insufficient distribution alignment. To solve this problem, we propose the use of Initial Pseudo Labels (IPLs) generated through Adaptive Bandwidth-based Mean Shift Clustering (ABMSC), which are then refined using cosine similarity with unlabeled target data, bolstering SF-UDA’s efficiency. Furthermore, we introduce Weight-Aware Regularization (W-AR) to effectively mitigate negative transfer. Experimental results show significant accuracy improvements, with gains of 1.5%-6.7% and 1.3%-5% in the same operating environment, and 0.4%-24.8% and 3.1%-8.6% in different operating environments.