Integrating radiative and evaporative cooling shows promise for enhancing passive cooling, but durable self-curing integrated cooling paints remain underdeveloped. We designed a modified cementitious structure with advanced thermal-optical and mass transfer properties, boosting cooling power while ensuring durability, mechanical strength, and broad adhesion. The paint achieves 88 to 92% solar reflectance (depending on wetting), 95% atmospheric window emittance, ~30% water retention, and self-replenishing properties, maintaining stable optical performance even when wet. Field tests in tropical Singapore demonstrated superior cooling performance compared with commercial white paints. Pilot-scale demonstrations highlighted consistent electricity savings under varying weather conditions, supported by theoretical modeling. By leveraging sustainable water evaporation and thermal radiation, this paint offers a practical and long-term solution for mitigating the urban heat island effect.

Hardware implementation of reconfigurable and nonvolatile photoresponsivity is essential for advancing in-sensor computing for machine vision applications. However, existing reconfigurable photoresponsivity essentially depends on the photovoltaic effect of p-n junctions, which photoelectric efficiency is constrained by Shockley-Queisser limit and hinders the achievement of high-performance nonvolatile photoresponsivity. Here, we employ bulk photovoltaic effect of rhombohedral (3R) stacked/interlayer sliding tungsten disulfide (WS₂) to surpass this limit and realize highly reconfigurable, nonvolatile photoresponsivity with a retinomorphic photovoltaic device. The device is composed of graphene/3R-WS₂/graphene all van der Waals layered structure, demonstrating a wide range of nonvolatile reconfigurable photoresponsivity from positive to negative ( ± 0.92 A W⁻¹) modulated by the polarization of 3R-WS₂. Further, we integrate this system with a convolutional neural network to achieve high-accuracy (100%) color image recognition at σ = 0.3 noise level within six epochs. Our findings highlight the transformative potential of bulk photovoltaic effect-based devices for efficient machine vision systems.

With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS₂ and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrated circuits. Various ternary logic devices, including the standard ternary inverter (STI), negative ternary inverter (NTI), positive ternary inverter (PTI) and especially the ternary decrement cycling inverter (DCI), have been successfully implemented using the 2D materials. Then, by taking advantage of the optimized ternary adder algorithm and the novel ternary cycling inverter, we design a novel ternary ripple-carry adder with great circuitry simplicity. Our design shows about a 50% reduction in the required number of transistors compared to the existing ternary technology. This work paves a new way for the ternary integrated circuits design, and shows potential to fulfill higher logic data density and a smaller chip area in the future.

Multi-valued logic (MVL) circuits, especially the ternary logic circuits, have attracted great attention in recent years due to their higher information density than binary logic systems. However, the basic construction method for MVL circuit standard cells and the CMOS fabrication possibility/compatibility issues are still to be addressed. In this work, we propose various ternary arithmetic circuits (adders and multipliers) with embedded ternary arithmetic algorithms to improve the efficiency. Firstly, ternary cycling gates are designed to optimize both the arithmetic algorithms and logic circuits of ternary adders. Secondly, optimized ternary Boolean truth table is used to simplify the circuit complexity. Thirdly, high-speed ternary Wallace tree multipliers are implemented with task dividing policy. Significant improvements in propagation delay and power-delay-product (PDP) have been achieved as compared with previous works. In particular, the ternary full adder shows 11 aJ PDP at 0.5 GHz, which is the best result among all the reported works using the same simulation platform. And an average PDP improvement of 36.8% in the ternary multiplier is also achieved. Furthermore, the proposed methods have been successfully explored using standard CMOS 180nm silicon devices, indicating its great potential for the practical application of ternary computing in the near future.