The paper proposes a BIST approach for deriving the main characterization parameters of ADCs from histogram data. An adequate choice of input stimuli and time decomposition scheme is proposed in order to minimize the extra on-chip hardware required to extract these parameters. The idea of time decomposition consists in replacing classical hardware-consuming concurrent calculations by hardware-saving time-spread calculations. The decomposition technique is used both at high level (specific test phases are dedicated to each ADC parameter computation) and low level (sequential steps inside each test phase). Pseudo-algorithms are given to derive offset, gain error and nonlinearities.

A general BIST architecture for A-to-D converters involves the integration of both an analog test signal generator and a digital output response analyzer. This paper presents a structure for the internal generation of a linear signal used with the histogram-based test technique. The structure is based on two highly linear ramp generators together with a feedback control circuitry. Results show that the proposed structure preserves the linearity of the ramp generators while accuracy of the triangle-wave is provided by means of a calibration scheme.

This paper presents an alternate test implementation based on model redundancy that permits to achieve lower prediction errors than a classical implementation, even if training is performed over a small set of devices. The idea is to build different regression models for each specification during the training phase, and then to verify prediction consistency between the different models during the production testing phase. In case of divergent predictions, the devices are removed from the alternate test tier and directed to a second tier where further testing may apply. The approach is illustrated on a real case study that employs production test data from an RF power amplifier. Results show that, on the contrary to the classical implementation where prediction accuracy degrades when reducing the training set size, the proposed approach permits to preserve prediction accuracy independently of the training set size, while only a very small number of devices are directed to the second tier of the test flow.

In this paper, we investigate an alternate test strategy for RF integrated circuits based on DC measurements. A methodology to select the appropriate DC parameters is presented, that allows precise estimation of the DUT performances while minimizing the number of measurements to be carried out. The method is demonstrated both on simulation test data from a Low-Noise Amplifier (LNA) and production test data from a Power Amplifier (PA). Results indicate that good prediction of the RF performances can be achieved using only a reduced number of DC measurements.