Error injection has become critically important for testing the reliability of newly designed hardware systems. Evaluating how a Design Under Test (DUT) reacts to different error injection methodologies is essential for verification engineers to design dependable Universal Verification Methodology (UVM) scoreboards for error-detection purposes. The first main contribution of this paper is to decide on the feasibility and compatibility of some error injection techniques when used with Networks-on-Chip (NoC) platforms for simulation and hardware emulation environments. We target a UVM-based error injection and detection environment with reusable components. Proposed techniques, introducing both positive and negative test scenarios, are applied to two examples of NoC components: a base router and Daniel router. Base router is a simple case study to prove proposed schemes, whereas Danial router is a complex re-configurable open-source case study. Daniel router provides the ability to change router architecture with some parameters and applied algorithms. The second main contribution of the paper is to integrate a full UVM environment with various verification approaches. Approaches include error injection and detection using reusable and generic UVM environment and components for NoC. Network response is inspected according to error type and methodology. Finally, the proposed UVM environment is used to test and verify an N×N 2-D network composed of base routers or Daniel routers.

Key exchange is one of the major concerns in cryp-tology. Neural cryptography is a recent non-classical paradigm which achieves key exchange by mutual learning between two neural networks that receive the same input patterns and update their weights using specific rules. Each weight component of the network can be seen as a random walker in the weight space. The two walkers move in the weight space and reflect at two boundaries (left and right) which represent the network synaptic depth. The reflecting boundaries cause the distance between the two walkers decreases if one of them hits the boundary when a common direction is chosen at each step. Therefore, the mutual learning algorithm relies on this defined boundary condition to achieve synchronization between the two parties. In this paper, we aim to increase the security of the neural cryptography by authenticating the communication using preshared secrets. The mutual learning algorithm is modified so that the reflecting boundaries become hidden and only accessible by the two partners. New update rules are developed to exploit the secret information without adding any limitation to the initial configuration for the two parties. This is done by converting the two boundaries located at a straight line path to a one secret boundary located randomly at a circular path. Therefore, the mutual learning is impeded except this secret information is known. The proposed algorithm is called Neural Cryptography with Secret Boundaries (NCSB) and it is proved with information theory that the secret boundaries can not be revealed from the public information broadcast through the public channel.

Current research in interfacing clusters within Hierarchical Networks-on-Chip (HNoC) as well as interfacing NoC-based systems adopts a centralized approach. In this approach, a specific Processing Element (PE) acts as a gateway between interfacing peripherals and the rest of NoC elements. This paper evaluates this approach and show that it is not optimal for handling the inter-NoC communication. Routing inter-NoC traffic through a system to its gateway PE deteriorates the network performance. Results show that both the throughput and latency of the centralized approach degrade with the increase in the inter-NoC traffic bandwidth. To alleviate this, we propose a novel distributed approach, which separates the inter-NoC traffic from the intra-NoC one. Our approach relies on distributed buffers to allow PEs to efficiently communicate with the interfacing peripheral. We evaluate our approach against other interfacing ones using synthetic traffic as well as real benchmark applications. Our evaluation covers the whole system performance as well as its inter-and intra-NoC parts. Results prove that the proposed approach outperforms previous interfacing ones in terms of throughput and latency. The proposed approach significantly enhances the inter-NoC performance without any deterioration in the intra-NoC one. Considering the inter-NoC performance, we achieve a throughput that is close to the maximum possibly attainable one. Other approaches show major performance degradation, reaching as low as 10% of this maximum attainable throughput.