This paper presents approximate multipliers which are efficiently deployed on Field Programmable Gate Arrays (FPGAs) by using newly proposed approximate logic compressors at different levels of accuracy. Our approximate multiplier designs offer higher gains of power-delay-area products (PDAP) than those of the state-of-the-art works at comparable accuracies. Furthermore, in terms of delay, occupied area, and dynamic power dissipation, our designs are much better than Lookup Table based multiplier Intellectual Properties that are available on an FPGA. Particularly, our proposed 8-, 16-, and 32-bit multipliers can deliver PDAP gains up to 7.1×, 8.3×, and 5.0×, respectively. The effectiveness and applicability of our designs are also demonstrated by image processing applications such as image multiplication and sharpening. The experiments show that for the image sharpening, our 8×8 multipliers can deliver a good peak signal-to-noise ratio (PSNR) of 46.81 dB, a structural similarity index metric (SSIM) of 0.9989, and a dynamic power saving of up to 36.7% with regard to the exact multiplier. For the image multiplication, approximate 16×16 multipliers can offer a high PSNR of 80.25 dB, an SSIM of 1.0, and a dynamic power saving of up to 58.15%. From these demonstrations, the proposed multipliers are expected to be appropriate with high-performance and low-power error-resilient applications.

This paper presents a methodology for digital switching noise suppressions on the power lines at a fundamental frequency as well as its harmonics by using a clock scheduling technique in the frequency domain. Our approach provides a deep insight of the clock scheduling at the arbitrary phase shifts of clock signals. Moreover, an optimization algorithm is applied to find an optimal phase shift of a clock signal in order to maximize noise suppressions at a specific frequency band. The experimental results on a Xilinx field-programmable gate array Spartan-3 (XC3S400-TQ144) show that the estimated noise reduction rates well-match the measured ones. In these tests, dummy logics are used as noise injectors. This paper also presents a design example with a data encryption standard cryptoprocessor to demonstrate the applicability of our approach. The experiments show that the highest error between the estimated and the measured results is about 2.5 dB. Interestingly, our approach seems to be appropriately used with the designs in wireless communications where designers address to minimize the digital switching noise at the specific frequency bands of interest.

Detection and alarm of leakage of hydrogen (H2) gas is an extremely important issue needed to be addressed. In this study, we fabricated and calibation portable devices based on the H2 sensor using SnO2 thin film with Pd nanoscale catalytic as a sensing layer. For practical application of the sensor, we designed and realized PCB circuit boards, microprocessors, data processing, output signals, data storage, power sources and source code. This sensor based portable devices were able to monitor to as low as 25 ppm H2 gas. Power consumption and selectivity of the sensor were also investigated. This study will open another simple and low-cost approach to monitor toxic and flammable gases for environmental monitoring.

Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

Nowadays, integrated circuits (ICs) have higher integration densities. The simultaneous switching activities that are synchronized with a single global clock is one of the main causes that produce voltage drops across the power distribution network (PDN) of the ICs. Since the drop increase the delay of circuits, such drops may cause the timing failures that lead to the malfunctions of an IC. Therefore, a tool that supports for debugging the failures is essential. This paper presents a high-resolution supply voltage sensor that can be applicable for debugging timing failures at real-time, or determining the timing margins for the timing critical designs. Our supply voltage sensor is made up by using standard Look-up Table (LUT) cells, and dedicated carry cells with high-speed propagation delays. The experiments show that the voltage resolution of our supply voltage sensor is about 3.3mV on a Xilinx FPGA Spartan-6 (XC6SLX9).