This paper presents a universal serial bus (USB) transceiver with a serial interface engine (SIE) and an asynchronous first-in first-out (FIFO) queue for packet transformation and data transmission in field-programmable gate array (FPGA)-to-FPGA communication. The SIE block receives the data to be transmitted from the central processing unit of a PC and transfers those data to the universal transceiver macrocell interface, which handles data serialization and deserialization, bit stuffing, clock recovery, and clock synchronization. An asynchronous FIFO queue of 2 kilobits is designed to guarantee correct communication between two FPGA development boards. A parallel-in serial-out block converts parallel input data into serial data. A product identification (PID) check block determines whether the serial data are in the USB packet format. The cyclic redundancy check (CRC) checksums, namely CRC5 and CRC16, are presented with data check statements. After passing through the NRZI decoder, bit-unstuffing, PID check, and CRC16 blocks, the received serial data are converted into parallel output data by using a serial-in parallel-out block. The FPGA-to-FPGA communication design operates correctly. An application-specific integrated circuit (ASIC) of the USB transceiver is implemented using TSMC 0.18-μm CMOS technology. The gate counts, power consumption, operating frequency, and chip area of the ASIC are 14,547, 2.6742 mW, 50 MHz, and 0.7 × 0.67 mm2, respectively, at a supply voltage of 1.8 V and total pin number of 38.

This study presents a mixed-mode chip for use in a vector-controlled induction motor drive. It exhibits digital scalar space vector pulse width modulation (DSSVPWM), and comprises a proportional-integral (PI) controller, a simplified central processing unit (CPU), and a second-order delta-sigma analog-to-digital converter (Δ-Σ ADC). It is fabricated using a standard 0.35-μm 2P4M CMOS process. All of the circuits, digital and analog, are realized in a single chip as a convenient, high-speed, highly integrated, and low-cost solution. The digital circuit contains a DSSVPWM, a simplified CPU, a PI controller, and a decimator filter; the analog circuit is a second-order switched-current (SI) delta-sigma modulator, which includes two discrete-time integrators, a current comparator, a current-mode digital-to-analog converter, a D-type flip-flop, a nonoverlapping clock generator, and a bias current generator. This mixed-mode chip constitutes a closed-loop motor drive system with stable performance, short response times, precise controllability, and flexibility. Experimental results indicate that the digital circuit has a power consumption of 17.95 mW and a maximum frequency of 100 MHz, and that the SNR and power dissipation of the analog circuit are 71.9 dB and 12.1 mW, respectively, with a bandwidth of 10 kHz, an over sampling ratio of 128, and a sampling rate of 2.56 MHz at a power supply of 3.3 V.

This article proposes an Internet of Things–based smart home system composed of a virtualized cloud server and a mobile phone app. The smart Internet of Things–based system includes a sensing network, which is developed with the ZigBee wireless communication protocol, a message queuing telemetry transport, a virtualized cloud server and a mobile phone app. A Raspberry Pi development board is used to receive packet information from the terminal sensors using ZigBee wireless communication. Then, the message queuing telemetry transport broker not only completes transmission of the message but also publishes it to the virtualized cloud server. The transmission can then be viewed through the website using a mobile phone. The designed app combines the application of the virtualized cloud server, client sensors and the database. Verification experiments revealed the measured average response time and throughput of approximately 4.0 s and 6069 requests per second, respectively, for the virtualized web server and approximately 0.144 s and 8866 packets per second, respectively, for the message queuing telemetry transport broker. The designed functions of the mobile phone app are a global positioning system home monitoring, family memo, medical care and near-field communication key. Both interlinkage and handler methods are proposed to facilitate a powerful function without delay in displaying information. The proposed system integrates with software and hardware to complete the data analysis and information management quickly and correctly. It can cater to user needs with superior ease and convenience.

This study presents a radiofrequency (RF)-energy-harvesting integrated circuit (IC) for powering wireless sensor networks with a wireless transmitter with an industrial, scientific, and medical (ISM) of 915 MHz. The proposed IC comprises an RF-direct current (DC) rectifier, an over-voltage protection circuit, a low-power low-dropout (LDO) voltage regulator, and a charger control circuit. In the RF-DC rectifier circuit, a six-stage Dickson voltage multiplier circuit is used to improve the received RF signal to a DC voltage by using native MOS with a small threshold voltage. The over-voltage protection circuit is used to prevent a high-voltage breakdown phenomenon from the RF front-end circuit, particularly for near-field communication. A low-power LDO regulator is designed to provide stable voltage by using zero frequency compensation and a voltage-trimming feedback. Charging current is amplified N times by using a current mirror to rapidly and stably charge a battery in the proposed charger control circuit. The obtained results revealed that the maximum power conversion efficiency of the proposed RF-energy-harvesting IC was 40.56% at an input power of −6 dBm, an output voltage of 1.5 V, and a load of 30 kΩ. A chip area of the RF-energy-harvesting IC was 0.58 × 0.49 mm², including input/output pads, and power consumption was 42 μW.

This paper proposes an Ethernet packet transformation and transmission architecture between Modbus transmission control protocol (Modbus TCP) and universal serial bus (USB) 3.0 developed with a field-programmable gate array (FPGA) development kit. The proposed architecture is used to complete packet transformation and transmission between Ethernet and USB 3.0 for application in induction motor (IM) control. The Ethernet receiver receives and analyses Modbus TCP packets and sends the source address, destination address, IP header, and Modbus TCP header to the register to verify the correctness of the packet. The Modbus TCP packet is stored in static random access memory and awaits access through a USB 3.0 module. An FPGA development kit (Intel DE10-Standard) is used for functional verification. The measured results show that the latency, throughput, and dynamic power are 18.845 μs, 950.31 Mbps, and 142.17 mW, respectively, at a voltage of 1.8 V and an operating frequency of 125 MHz. The main advantage is that the proposed Ethernet and USB bridge performs high throughput and short latency with FPGA development kit and that an application specific integrated circuit (ASIC) is provided with low power consumption. The robustness and convenience of the proposed ASIC are especially advantageous. The motivation is to resolve an existing problem that Ethernet and USB operate on different platforms.