Mixed-criticality (MC) systems have recently been devised to address the requirements of real-time systems in industrial applications, where the system runs tasks with different criticality levels on a single platform. In some workloads, a high-critically task might overrun and overload the system, or a fault can occur during the execution. However, these systems must be fault tolerant and guarantee the correct execution of all high-criticality (HC) tasks by their deadlines to avoid catastrophic consequences, in any situation. Furthermore, in these MC systems, the peak-power consumption of the system may increase, especially in an overload situation and exceed the processor thermal design power (TDP) constraint. This may cause generating heat beyond the cooling capacity, resulting the system stop to avoid excessive heat and halting the processor. In this article, we propose a technique for dependent dual-criticality tasks in fault-tolerant multicore MC systems to manage peak-power consumption and temperature. The technique develops a tree of possible task mapping and scheduling at design-time to cover all possible scenarios and reduce the low-criticality task drop rate in the HC mode. At the runtime, the system exploits the tree to select a proper schedule according to fault occurrences and criticality mode changes. Experimental results show that the average task schedulability is 74.14% on average for the proposed method, while the peak-power consumption and maximum temperature are improved by 16.65% and 14.9 °C on average, respectively, compared to a recent work. In addition, for a real-life application, our method reduces the peak power and maximum temperature by up to 20.06% and 5 °C, respectively, compared to a state-of-the-art approach.

Energy consumption and predictability are two important constraints in designing real-time embedded systems and one of the recently proposed solutions for the energy consumption problem is the use of non-volatile memories due to their lower leakage power consumption. Furthermore, because of their non-volatile nature, the use of these memories helps normally-off computing and energy harvesting systems. However, the write access latency of non-volatile memories is considerably more than that of SRAM which can decrease the performance and predictability of the system. We present a predictable non-volatile data memory for real-time embedded systems which improves both worst-case execution time (WCET) and performance of the system using a hybrid hardware-software solution. As part of this solution, we add a special write buffer to the memory controller and adopt a multi-bank memory configuration which improves the overall latency of write operations. We also present a new low-overhead software-based optimization technique that makes the proposed system more predictable. Furthermore, we present the WCET analysis algorithm which can be used to estimate the WCET of applications during the design time. The results show that compared to a hybrid SRAM-NVM architecture, the proposed solution improves the WCET and performance by 33% and 47%, respectively.

The energy efficiency of emerging nonvolatile processors equipped with FRAM-SRAM memory makes them a promising solution for energy harvesting systems. To enable correct functionality and forward progress with an unreliable power supply, the system must accumulate sufficient energy in the capacitor to execute tasks atomically, even in the worst case scenario. Due to the large gap between the average and worst case energy consumption of tasks, state of the art approaches like eM-map require a large capacitor to execute tasks on the SRAM. However, the size, cost, and charging time of the capacitor are major concerns in the energy harvesting systems. In this paper, we proposed CHANCE, a capacitor charging management scheme that improves the capacitor size and average response time of an energy harvesting system. CHANCE analyses the energy consumption of tasks to set an appropriate capacitor size to make a balance between capacitor charging time and failure rate for each task. The results show that CHANCE improves the response time of state of the art approaches up to 68% with a five times smaller capacitor.

An increasing trend for reducing cost, space, and weight leads to modern embedded systems that execute multiple tasks with different criticality levels on a common hardware platform while guaranteeing a safe operation. In such mixed-criticality (MC) systems, multiple worst case execution times (WCETs) are defined for each task, corresponding to the system operation mode to improve the MC system’s timing behavior at runtime. Determining the appropriate WCETs for lower criticality (LC) modes is nontrivial. On the one hand, considering a very low WCET for tasks can improve the processor utilization by scheduling more tasks in that mode, on the other hand, using a larger WCET ensures that the mode switches (which causes by task overrunning) are minimized, thereby improving the quality of service for all tasks, albeit at the cost of processor utilization. Hitherto, no analytical solutions are proposed to determine WCETs in LC modes. In this regard, we propose a scheme to determine WCETs by the Chebyshev theorem, to make a tradeoff between the number of scheduled tasks at design-time and the number of dropped low-criticality tasks at runtime as a result of frequent mode switches. To have a tight bound of execution times and mode switching probability, we also propose a distribution analytics-based scheme, in which the mode switching probability is obtained based on the cumulative distribution function. Our experimental results show that our scheme improves the utilization of state-of-the-art MC systems by up to 72.27%, while maintaining 24.28% mode switching probability in the worst case scenario. Besides, the results of running embedded real-time benchmarks on a real platform show that the distribution-based scheme can improve the utilization by 7.30% while bounding the mode switching probability by 4.85% more, compared to the Chebyshev-based scheme.

Most modern multi-core edge devices work in outdoor situations with limited power supplies like energy harvester and batteries. Therefore, energy consumption is a fundamental issue in which the memory subsystem has a significant role. Scratchpad memories (SPM) can provide a broad potential for energy saving. Still, due to the insufficient SPM capacity in such edge devices, a rigorous SPM data allocation scheme is necessary to reduce the energy consumption of the memory subsystem. Emerging non-volatile memories (NVMs) are very useful to reduce the energy consumption of the memory subsystem. Therefore, embedded and edge devices can take advantage of hybrid SPM composed of both NVM and SRAM to achieve further energy saving. This paper proposes MASTER, a task mapping, task scheduling, and dynamic SPM allocation scheme that efficiently utilizes the hybrid SPM space. To this end, we model the hybrid SPM allocation on a multi-core system with integer linear programming formulation to minimize the energy consumption of the memory subsystem. Experimental results show that MASTER improves the energy saving of the memory subsystem by up to 34% compared to EADA, which is a heuristic dynamic data allocation algorithm for multi-core systems with hybrid SPM.