Electrochemical etching is a promising wet etching technology for preparing porous structures and the flat surface etching of 4H-SiC. In this study, the effects of current density and KOH concentration on the etching of 4H-SiC were investigated. We found that the respective mechanisms for preparing porous structures and flat surface etching differed. The porous and flat etching modes were proposed to clarify the mechanistic differences. In addition, we achieved an etch rate of 1 μm h⁻¹ in flat etching mode, and the sample surface was improved for 4H-SiC applications in the field of optoelectronics and microelectronics through the thermal oxidation of SiC.

Wide band gap semiconductor 4H-SiC is currently widely used in the manufacture of high-frequency and high-voltage power devices. The size of commercial 4H-SiC wafers is increasing, from 4 inches to 6 inches. Surface roughness, as one of the parameters reflecting the quality of epitaxial wafers, is closely related to the performance of power devices. Most studies on the uniformity of epitaxial layers did not focus on RMS; however, the uniformity of epitaxial surface roughness also affects the device yield. In this paper, the root mean square roughness (RMS) and uniformity (σ) of epitaxial wafers are investigated as a function of epitaxy conditions, including C/Si ratio, growth temperature, and Si/H ratio. It was found that the best values of RMS and σ were obtained with C/Si ratio = 1 in the experimental range. Growth temperature had opposite effects on RMS and σ, with better RMS uniformity obtained at lower growth temperatures. An insignificant effect on RMS and σ has been found with the Si/H ratio changes in the experimental range. We hope that our experiments can play a certain role in promoting the improvement of the surface roughness of wafer-scale 4H-SiC epitaxial layers.

Due to the special ‘step-controlled epitaxy’ mode of 4H-SiC, it is easy to generate step bunching on the surface. Although the flatness of epitaxial wafers has been greatly improved with the advancement of epitaxy technology, there are still localized steps on the surface of some certain wafers. The presence of localized steps can affect the performance of the subsequently fabricated devices. Therefore, minimizing or even eliminating the local steps of the epitaxial surface to obtain an atomically smooth surface is very important. Here, we utilize a high-temperature oxidation process to reduce the size of the giant steps and obtain a flatter epitaxial surface. We found that oxidation parameters such as temperature, pressure, and time play an important role in the surface planarization, and the degree of planarization can be further improved by multiple oxidation processes. In addition, although the oxidation rate under low pressure is lower than that under atmospheric pressure, a smoother epitaxial surface can be obtained. Our results demonstrate the possibility of obtaining atomically smooth surfaces through a high-temperature oxidation process.

Wafer-scale on-axis 4H-SiC epitaxial layers with very low roughness were obtained in this study. By performing carbon-rich hydrogen etching and epitaxial growth of the epitaxial layer at different temperatures, local mirror regions (LMRs) with root mean square (RMS) roughness less than 0.2 nm were obtained on the epitaxial layer surface. The LMRs’ length is tens of millimeters, and the width is sub-millimeters. The step-flow growth induced by threading screw dislocations (TSDs) was observed on the epitaxial layer surface by atomic force microscopy (AFM), together with the double bi-atomic step-flow growth induced by the step bunch, which was the cause of LMRs. Furthermore, the growth mechanism was investigated by wet etching. The etching pits were found to be associated with 3C-SiC and their effect on the growth rate of epitaxial layers was further explored.