The c-myc gene is induced upon growth factor stimulation of arrested cells. The interaction of a mitogen with a transmembrane receptor triggers a variety of parallel signal transduction cascades. In order to analyse the role of the Ras/Raf cascade in the regulation of c-myc expression we have established fibroblast cell lines harboring conditional systems activating or inhibiting this pathway. Fusion of the c-Raf-1 kinase domain with the hormone binding domain of the estrogen receptor (c-Raf-1-BxB-ER^TM) provides a 4-hydroxytamoxifen regulated form of the oncogenic c-Raf-1 kinase. We have generated NIH3T3 cells stably expressing the chimeric Raf protein (N-BxB-ER^TM). 4-hydroxytamoxifen mediated activation of the fusion protein in serum starved N-BxB-ER^TM induces the expression of the c-myc gene within 2 – 6 h. Deletion of the c-Raf-1 kinase domain generates a mutant c-Raf-1 protein (c-Raf-1-C4B), which can directly interact with the effector domain of the Ras protein and thereby block Ras mediated signalling. We have established a NIH3T3 based cell line expressing the c-Raf-1-C4B protein under the control of a tetracycline responsive promoter (N-C4B-tet). Serum starved cells expressing the c-Raf-1-C4B protein exhibit a significantly reduced induction of c-myc expression following serum stimulation compared to the same cells not expressing the Ras inhibitor. The induction of c-myc mRNA following the activation of the isolated Raf/Mek/Erk cascade in addition to the partial inhibition of serum mediated induction of c-myc expression in the presence of the Ras inactivating c-Raf-1-C4B mutant strongly indicates an involvement of the Ras/Raf pathway in the regulation of c-myc expression.

Deep learning such as Convolutional Neural Networks (CNNs) are an important workload increasingly demanding high-performance hardware acceleration. One distinguishing feature of deep learnng workload is that it is inherently resilient to small numerical errors and works very well with low precision hardware. Thus we propose a novel method, called Double MAC, to theoretically double the computation rate of CNN accelerators by packing two multiply-and-accumulate (MAC) operations into one DSP block of off-the-shelf FPGAs. There are several technical challenges, which we overcome by exploiting the mode of operation in the CNN accelerator. We have validated our method through FPGA synthesis and Verilog simulation, and evaluated our method by applying it to the state-of-the-art CNN accelerator. We find that our Double MAC approach can increase the computation throughput of a CNN layer by twice. On the network level (all convolution layers combined), the performance improvement varies depending on the CNN application and FPGA size, from 14% to more than 80% over a highly optimized state-of-the-art accelerator solution, without sacrificing the output quality significantly.

Resistive crossbar arrays, despite their advantages such as parallel processing, low power, and high density, suffer from the sneak path problem created by IR voltage drops. The crossbar non-idealities considerably degrade the accuracy of matrix multiplication operation, which is the cornerstone of hardware accelerated neural networks. In this paper, we propose a novel technique to capture the sneak path problem to enable off-chip learning and weight transfer. The proposed technique can be easily integrated into any neural network training framework. Performance results show a significant improvement after retraining the network with the proposed mask technique. Two mask solutions have been proposed and studied to capture the sneak path problem in resistive crossbar arrays. Both mask solutions were successfully able to achieve classification accuracy close to the baseline accuracy. The tradeoffs between the two solutions are discussed and compared in terms of accuracy, power, and area.

Resistive Crossbar Arrays present an elegant implementation solution for Deep Neural Networks acceleration. The Matrix-Vector Multiplication, which is the corner-stone of DNNs, is carried out in O(1) compared to O(N2) steps for digital realizations of O(log2(N)) steps for in-memory associative processors. However, the IR drop problem, caused by the inevitable interconnect wire resistance in RCAs remains a daunting challenge. In this paper, we propose a fast and efficient training and validation framework to incorporate the wire resistance in Quantized DNNs, without the need for computationally extensive SPICE simulations during the training process. A fabricated four-bit Au/Al2O3/HfO2/TiN device is modelled and used within the framework with two-mapping schemes to realize the quantized weights. Efficient system-level IR-drop estimation methods are used to accelerate training. SPICE validation results show the effectiveness of the proposed method to capture the IR drop problem achieving the baseline accuracy with a 2% and 4% drop in the worst-case scenario for MNIST dataset on multilayer perceptron network and CIFAR 10 dataset on modified VGG and AlexNet networks, respectively. Other nonidealities, such as stuck-at fault defects, variability, and aging, are studied. Finally, the design considerations of the neuronal and the driver circuits are discussed.

Stochastic computing (SC) is a promising computing paradigm for applications with low precision requirement, stringent cost and power restriction. One known problem with SC, however, is the low accuracy especially with multiplication. In this paper we propose a simple, yet very effective solution to the low-accuracy SC-multiplication problem, which is critical in many applications such as deep neural networks (DNNs). Our solution is based on an old concept of sign-magnitude, which, when applied to SC, has unique advantages. Our experimental results using multiple DNN applications demonstrate that our technique can improve the efficiency of SC-based DNNs by about 32X in terms of latency over using bipolar SC, with very little area overhead (about 1%).