Inductive-peaking-based bandwidth extension techniques for CMOS amplifiers in wireless and wireline applications are presented. To overcome the conventional limits on bandwidth extension ratios, these techniques augment inductive peaking using capacitive splitting and magnetic coupling. It is shown that a critical design constraint for optimum bandwidth extension is the ratio of the drain capacitance of the driver transistor to the load capacitance. This, in turn, recommends the use of different techniques for different capacitance ratios. Prototype wideband amplifiers in 0.18-mum CMOS are presented that achieve a measured bandwidth extension ratio up to 4.1 and simultaneously maintain high gain (>12 dB) in a single stage. Even higher enhancement ratios are shown through the introduction of a modified series-peaking technique combined with staggering techniques. Ultra-wideband low-noise amplifiers in 0.18-mum CMOS are presented that exhibit bandwidth extension ratios up to 4.9

A fully integrated switched-capacitor power amplifier (SCPA) utilizes switched-capacitor techniques in an EER/Polar architecture. It operates on the envelope of a nonconstant envelope modulated signal as an RF-DAC in order to amplify the signal efficiently. The measured maximum output power and PAE are 25.2 dBm and 45%, respectively. When amplifying an 802.11g 64-QAM orthogonal frequency-division multiplexing (OFDM) signal, the measured error vector magnitude is 2.6% and the average output power and power-added efficiencies are 17.7 dBm and 27%, respectively.

A switched-capacitor power amplifier (SCPA) that realizes an envelope elimination and restoration/polar class-G topology is introduced. A novel voltage-tolerant switch enables the use of two power supply voltages which increases efficiency and output power simultaneously. Envelope digital-to-analog conversion in the polar transmitter is achieved using an SC RF DAC that exhibits high efficiency at typical output power backoff levels. In addition, high linearity is achieved and no digital predistortion is required. Implemented in 65 nm CMOS, the measured peak output power and power-added efficiency (PAE) are 24.3 dBm and 43.5%, respectively, whereas when amplifying 802.11g 64-QAM OFDM signals, the average output power and PAE are 16.8 dBm and 33%, respectively. The measured EVM is 2.9%.

A class-G supply modulator utilizes parallel low- dropout (LDO) regulators that are controlled by comparators and negative feedback. It optimizes the power consumption of a nonlinear power amplifier (PA) operating with supply modulation, such that it draws current from one of multiple appropriately sized supply voltages as determined by the input signal envelope. The class-G modulator is used in conjunction with a class-E PA operating in an envelope elimination and restoration (EER) mode to efficiently amplify signals with large peak-to-average ratios. The measured maximum output power and power added efficiency (PAE) are 29.3 dBm and 69%, respectively. The class-G technique is demonstrated for a 64 QAM, OFDM input signal (symbol period = 4 mus) wherein the measured error vector magnitude (EVM) is 2.5% and the average efficiency of 22.6%.

A class-E power amplifier (PA) utilizes differential switches and a tuned passive output network improves power-added efficiency (PAE) and insensitivity to amplitude variations at its input. A modulator is introduced that takes outphased waveforms as its inputs and generates a pulse-width and pulse-position modulated (PWPM) signal as its output. The PWPM modulator is used in conjunction with a class-E PA to efficiently amplify constant envelope (e.g., GMSK) and non-constant envelope (e.g., QPSK, QAM, OFDM) signals with moderate peak-to-average ratios (PAR). The measured maximum output power of the PA is 28.6 dBm with a PAE of 28.5%, and the measured error vector magnitude (EVM) is 1.2% and 4.6% for GMSK and pi/4-DQPSK (PAR ap 4 dB) modulated signals, respectively.

This paper presents an all-digital class-G quadrature switched-capacitor power amplifier (Q-SCPA) implemented in 65 nm CMOS. It combines in-phase (I) and quadrature (Q) signals on a shared capacitor array. The I/Q signals are digitally weighted and combined in the charge domain. Quadrature summation results in a 3 dB signal loss; Hence the Q-SCPA utilizes a class-G dual-supply architecture to improve efficiency at backoff. Unlike polar/EER counterparts, the Q-SCPA requires no wideband phase modulator or delay matching circuitry. The Q-SCPA delivers a peak output power of 20.5 dBm with a peak PAE of 20%. It is measured with a 10 MHz, 64 QAM LTE signal, and achieves an ACLR of <;-30 dBc, with an EVM <; 4%-rms.