Convolutional neural network (CNN) offers significant accuracy in image detection. To implement image detection using CNN in the Internet of Things (IoT) devices, a streaming hardware accelerator is proposed. The proposed accelerator optimizes the energy efficiency by avoiding unnecessary data movement. With unique filter decomposition technique, the accelerator can support arbitrary convolution window size. In addition, max-pooling function can be computed in parallel with convolution by using separate pooling unit, thus achieving throughput improvement. A prototype accelerator was implemented in TSMC 65-nm technology with a core size of 5 mm². The accelerator can support major CNNs and achieve 152GOPS peak throughput and 434GOPS/W energy efficiency at 350 mW, making it a promising hardware accelerator for intelligent IoT devices.

An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces. By implementing the sequential analog fabric (SAF), the engine’s mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28nm CMOS technology and occupies 0.68mm². The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem – classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.

Recently, the Bird's-Eye-View (BEV) representation has gained increasing attention in multi-view 3D object detection, demonstrating promising applications in autonomous driving. Although multi-view camera-based systems can be deployed at a low cost, high-performance multi-view BEV object detectors still require significant computational resources. Knowledge Distillation (KD) is one of the most practical techniques to train smaller yet accurate models. Different from image classification tasks, BEV 3D object detection approaches are more complicated and consist of several components. Therefore, in this paper, we propose a unified framework named BEV-LGKD to transfer knowledge in a teacher-student manner However, directly applying the teacher student paradigm to BEV features fails to achieve satisfying results due to heavy background information in RGB cameras. To solve this problem, we propose to leverage the localization advantage of LiDAR points. Specifically, we transform the LiDAR points into BEV space and generate the view-dependent foreground masks for the teacher-student paradigm. It is noted that our method only uses LiDAR points to guide the KD between RGB models. As the quality of depth estimation is crucial for BEV perception, we further introduce depth distillation to our framework. We have conducted comprehensive experiments on nuScenes dataset, bringing a maximum improvement of +3.4 mAP and +7.7 NDS for the student model. The code will be released at https://github.com/NorthSummer/LGKD

Existing deep convolutional neural networks (CNNs) generate massive interlayer feature data during network inference. To maintain real-time processing in embedded systems, large on-chip memory is required to buffer the interlayer feature maps. In this paper, we propose an efficient hardware accelerator with an interlayer feature compression technique to significantly reduce the required on-chip memory size and off-chip memory access bandwidth. The accelerator compresses interlayer feature maps through transforming the stored data into frequency domain using hardware-implemented $8\times 8$ discrete cosine transform (DCT). The high-frequency components are removed after the DCT through quantization. Sparse matrix compression is utilized to further compress the interlayer feature maps. The on-chip memory allocation scheme is designed to support dynamic configuration of the feature map buffer size and scratch pad size according to different network-layer requirements. The hardware accelerator combines compression, decompression, and CNN acceleration into one computing stream, achieving minimal compressing and processing delay. A prototype accelerator is implemented on an FPGA platform and also synthesized in TSMC 28-nm COMS technology. It achieves 403GOPS peak throughput and $1.4\times \sim 3.3\times $ interlayer feature map reduction by adding light hardware area overhead, making it a promising hardware accelerator for intelligent IoT devices.

Compute-in-memory (CIM) is a promising approach to solving the memory-wall problem existing in traditional computing architectures. In this paper, we introduce SSM-CIM, a charge-domain, static random-access memory (SRAM)-based CIM macro designed for area-energy-efficient convolutional neural network (CNN) inference. SSM-CIM utilizes an original sign-magnitude data encoding method for both inputs and weights. By codesigning four adjacent SRAM computing cells and employing a 3-bit digital-to-analog converter (DAC), SSM-CIM performs accurate 4-bit multiply-and-accumulate (MAC) computation in a single step, eliminating the peripheral digital shift-and-add circuits. To digitize the MAC computing results, a dedicated multi-reference assisted SAR ADC is designed by reusing the reference voltages from the DAC, which offers significant power and area savings. In addition, analog computing errors and quantization errors are analyzed to ensure the multi-bit computing accuracy of SSM-CIM. SSM-CIM is implemented and evaluated using 28-nm global foundry process. The post-layout simulation results validate the excellent computing linearity and accuracy of SSM-CIM. Benefitting from the compact layout design and fully parallel computing flow, the $144\times 256$ macro achieves a peak throughput of 2.3 TOPS, an area efficiency of 10.2 TOPS/mm2, and an energy efficiency of 205.4 TOPS/W with 4-bit weights and 4-bit inputs.

This article presents a four-lane single-ended transceiver featuring a crosstalk-canceling coding scheme, Fibonacci coding (FC), which supports high-speed transmission over high-density parallel inter-chip channels. In-depth experiments and analyses are presented to evaluate FC’s performance, and the results suggest that the FC scheme can provide significant near-end and far-end crosstalk cancellation (XTC) while maintaining high channel density for high-speed multi-lane inter-chip links. By simulation, an effective data rate of 4 $\times$ 8.5 Gb/s is enhanced to 3 $\times$ 18 Gb/s by FC for a four-channel link. The transceiver, including an FC codec, a feed-forward equalizer (FFE), and a continuous-time linear equalizer (CTLE), is implemented in 28-nm CMOS. It achieves a data rate density of 0.90 Tb/s/in with an energy efficiency of 1.29 pJ/b and an area of 0.004 mm $^{2}$ /lane. The performance of FC is measured on 3.8-mil-spaced four-lane coupled printed circuit board (PCB) microstrips. For the 2-in wires, the peak-to-peak jitter of the received eye is reduced by 45.0% at 10 Gb/s, and the horizontal aperture is broadened to 0.58 UI at a bit error rate (BER) $<$ 10 $^{-12}$ by activating the FC scheme and equalizers. For the 5-in wires, the jitter is reduced by 43.9% and the eye is 0.47-UI-wide at 8.5 Gb/s. And for the 8-in wires, the jitter is reduced by 49.0% and the eye is 0.43-UI-wide at 6 Gb/s.