This letter describes the design of a 6–21 GHz monolithic microwave integrated circuit (MMIC) low-noise amplifier (LNA) for ultra wideband (UWB) communication systems. At lower power consumption, a higher and flat gain of 23 $\pm $ 0.8 dB is achieved through the novel current-reuse configuration. The degeneration inductor and matching network are utilized to realize the simultaneous optimum matching for noise and input. The proposed LNA in 0.15 $\mu \text{m}$ GaAs pHEMT process achieves 1.03–1.76 dB noise figure (NF) and input return loss of more than 13 dB simultaneously. The LNA exhibits output return loss of more than 8 dB and output 1 dB compression point (OP $_{1\,\text{dB}}$ ) of 9.5–13.6 dBm, $-$ 2.5 to 2 dBm IIP3. The fabricated LNA consumes 135 mW from a 5 V supply and occupies a chip area of 1.3 $\times$ 0.8 mm.

This letter presents a three-stage current-reuse (CR) low-noise amplifier (LNA) monolithic microwave-integrated circuit (MMIC) design for broadband applications. The proposed LNA employs virtual ground and resistive feedback to achieve bandwidth extension and low noise. With the proposed techniques, the LNA is fabricated using a 0.15- $\mu$ m E-mode GaAs pseudomorphic high-electron-mobility transistor (pHEMT) process. The measurement results show a peak gain of 27.1 dB with a 3-dB bandwidth of 6–24 GHz and a dc power consumption of 130 mW. The noise figure (NF) of 0.71–1.9 dB, 9.2–12.6 dBm OP1dB, and 20–23.5 dBm OIP3 are achieved. The fabricated LNA, including the testing pads, has a chip size of 1.3 $\times$ 0.8 mm.

This letter presents a high-power amplifier (HPA) monolithic microwave integrated circuit (MMIC) based on the 0.25- $\mu$ m gallium nitride (GaN) high-electron-mobility transistor (HEMT) process. An elliptic filter output matching network (MN) and a matching circuit design method based on the combination of port impedance model (PIM) and load pull are proposed, which can achieve high harmonics suppression across 7–13 GHz using a reactive matching (RM) technique. The three-stage GaN PA achieves a minimum output power of 44.7 dBm and a peak output power of 46.3 dBm at 7.5 GHz. The power-added efficiency (PAE) is more than 34.4%, with a peak PAE of 39.0% at 9.5 GHz. The second harmonic suppression (HS2) reaches more than 22.5 dBc. The PA chip occupies an area of 4.8 $\times$ 3.0 mm $^{2}$ .

This paper presents an ultra-wideband 4–22 GHz three-stage low noise amplifier (LNA) that utilizes negative load impedance (NLI) and frequency compensation (FC) in the inter-stage matching network (ISMN). The NLI can effectively boost high-frequency (HF) gain and extend HF bandwidth (BW) and also suppress latter-stages noise, which further improves the overall design trade-off among gain, BW, and noise figure (NF). The FC expands low-frequency (LF) BW and improves gain flatness. Additionally, this paper presents the triple-resonant S22 design methodology that can effectively extend the output return loss BW of a common-source transistor with inductive degeneration. Fabricated in a 0.15- $\mu$ m E-mode GaAs pseudomorphic high electron-mobility transistor (pHEMT) process, the LNA achieves a remarkable 0.8–1.5 dB NF, $<$ -9 dB input return loss, $<$ -10 dB output return loss, 11.1–15 dBm OP1dB, 23–27.5 dBm OIP3 and 28–31 dB gain across the 4–22 GHz while drawing 50 mA from a 3.3 V supply.

In this paper, a methodology for designing a distributed model for coplanar asymmetry transformer on gallium nitride (GaN) process is proposed, which can accurately characterize the transformer’s feature up to a millimeter-wave band. The paper analyses a transformer-based matching circuit and proposes a practical transformer design procedure. A two stage, transformer matching based X-band power amplifier (PA) is reported here. Using the proposed transformer model and correlated transformer design procedure can sharply reduce schematic design period and optimum process time. The PA chip is designed on a 0.25 µm GaN technology process and occupies a 1.515 mm² area. At a 28 V supply, the gain and output power of the PA reaches 15 dB and 29 dBm respectively, and the wideband matching transformer reaches 47.6% bandwidth. To the best of our knowledge, the distributed model for coplanar asymmetry transformer and transformer-based X-band MMIC PA on GaN process in this work is the first case among the reported papers.

This article presents a design methodology in the high-order Chebyshev filter (HOCF) that realizes eight-way power synthesis and impedance conversion in the ultrawideband (UWB) high-power amplifier (HPA). The high-order filter (HOF) matching network (MN) absorbs parasitic capacitance and necessary supply inductors, which eliminates the difference between theoretical analysis and implementation. As a design example, a filter-based output MN (OMN) and interstage MN (ISMN) are achieved, which provides impedance transformation and power combination/division. The OMN and ISMN are parameterized, which can indicate the impedance mismatch and provide the correct target for impedance tuning. Based on the above, a UWB 5.5–18-GHz high-gain and HPA is implemented in 0.25- $\mu $ m gallium nitride (GaN) pHEMT technology. The three-stage HPA achieves an average output power of 16.25 W, with a small signal gain of 25–27.5 dB. The average power-added efficiency (PAE) is 21%, with a peak PAE of 23% at 11 GHz. The PA chip occupies an area of $3.7\times 4.2~\text {mm}^{2}$ .