A three-phase voltage source converter (VSC) is the most common power electronic device in power systems, but its inherent nonlinearity leads to complex AC-DC harmonic coupling phenomena. Existing studies focus on the harmonic coupling characteristics of three-phase VSCs under three-phase symmetrical conditions, but the problem under asymmetrical conditions is rarely investigated. This paper proposes a practical modeling method for harmonic state space (HSS) modeling of the VSC topology, together with a classic T/4-delay-based decoupled double synchronous reference frame (DDSRF) control system. The steady-state phase shift characteristics of the T/4 delay link for each frequency component are first analyzed, and the expansion method of the DDSRF controller in the HSS frame is derived. Compared with the conventional method, the proposed technique can provide an accurate description of the steady-state effect of the delay link without introducing additional state variables and, therefore, can reduce model complexity and computation burden. Then, the small-signal close-loop HSS model of the VSC is established, and a harmonic transfer matrix between the AC positive sequence/negative sequence and DC current of different frequencies is developed, which reveals the global harmonic coupling relationship between AC and DC grids across the VSC. Analysis shows that the T/4-delay-link significantly weakens the AC-DC inter-harmonic coupling near the fundamental frequency. Finally, the electromagnetic transient simulations are carried out based on MATLAB/Simulink, and the validity of the proposed modeling method and the model and the correctness for the analysis of harmonic coupling characteristics are verified.

The series-connected chain MMC with DC-blocking capacitor (C-SCMMC) is an emerging topology for HVDC tapping applications with high voltage and relatively low power capacity. However, the DC-blocking capacitor can be bulky and costly, which deteriorates its economy and flexibility. This paper investigates the feasibility of DC-blocking capacitor reduction, with special emphasis on the characteristics, control, and parameter design. The principle of C-SCMMC considering the DC-blocking capacitor dynamics is firstly modeled and analyzed, and the ripples and harmonics, as well as their influences on the external performance of the converter, are analyzed; then, improved control strategies, namely, the grid-tied harmonics suppression and current control, are proposed considering the enlarged DC-blocking capacitor voltage ripple; after that, the influence of reduced DC-blocking capacitor on the operation range and parameter design are analyzed, and the economic advantage is demonstrated via parameter design and comparison based on a typical bench mark. Analysis shows that the DC-blocking capacitor voltage ripple is coupled with other parameters, such as the arm output voltage and SM capacitance, and the advised range is from 0.1 to 0.3 p.u. at unity power factor to reduce the overall cost. In a typical design, the C-SCMMC can reduce the number of SMs by 2/3 and the capacitor energy storage capacity by 15% compared to the conventional MMC. Finally, simulation results obtained in MATLAB/Simulink 2024b are provided to verify the feasibility of the proposed converter and the correctness of the parameter design.