The rapid advancement of artificial intelligence (AI) has brought significant benefits across various domains, yet it has also led to increased energy consumption and environmental impact. This paper positions Green AI as a crucial direction for future research and development. It proposes a comprehensive framework for understanding, implementing, and advancing sustainable AI practices. We provide an overview of Green AI, highlighting its significance and current state regarding AI’s energy consumption and environmental impact. The paper explores sustainable AI techniques, such as model optimization methods, and the development of efficient algorithms. Additionally, we review energy-efficient hardware alternatives like tensor processing units (TPUs) and field-programmable gate arrays (FPGAs), and discuss strategies for designing and operating energy-efficient data centers. Case studies in natural language processing (NLP) and Computer Vision illustrate successful implementations of Green AI practices. Through these efforts, we aim to balance the performance and resource efficiency of AI technologies, aligning them with global sustainability goals.
5 January 2024 in Journal of Parallel and Distributed Computing
Smartphones have rapidly become ubiquitous with more than five billion users worldwide. Equipped with advanced sensors such as GPS, cameras, and microphones, they generate large amounts of diverse data. Much of this data, including locations, call logs, images, and online activities, is private. A suitable model training architecture is required to enhance usability through intelligent applications while preserving data privacy and security. In this paper, we develop a communication-efficient federated learning (CEFEEL) framework for smartphone personal assistant applications to protect data privacy and maintain user experience with low communication and computational overhead. The proposed framework identifies parameters that have converged early in the training phase and hence can be frozen or communicated intermittently, reducing communication overhead without compromising model accuracy. Extensive experiments demonstrate the robustness of our approach against unbalanced and non-IID data distributions. The experiments show that our developed framework, named FedFreeze and FedFreeze+ techniques, outperforms state-of-the-art FL algorithms like FedAvg in reducing communication and computational costs, preserving privacy, and maintaining training efficiency with comparable accuracy.
1 January 2025 in Journal of Electrical and Computer Engineering
On‐chip caches occupy a significant portion of modern processors, making them increasingly vulnerable to soft errors as technology scales. While data arrays often receive robust protection via error‐correcting codes (ECCs), metadata elements such as tag fields and status bits remain inadequately protected despite their critical role in ensuring memory integrity. This paper proposes two lightweight techniques to enhance cache metadata reliability: (1) a robust three‐bit encoding scheme for status bits that tolerates single‐bit flips without data corruption and (2) a selective tag replication scheme for dirty cache blocks, enabling reliable recovery from single‐bit errors in tag arrays. Simulation results on SPEC 2006 benchmarks show that our approach recovers 97.3% of injected soft errors in cache metadata, outperforming conventional SECDED protection (93.8%) with significantly lower overhead. The proposed design incurs only 0.50% area and 1.67% dynamic power overhead on a data L1 cache. Moreover, the proposed techniques can be extended to support common cache coherence protocols in multicore systems with minimal modification.