This letter reports a novel back-to-back E-shaped defected ground structure (DGS) and two-side loading scheme for miniaturized dual-band substrate integrated waveguide (SIW) bandpass filter (BPF) designs. The SIW loaded by novel DGS supports evanescent-mode wave propagation below the cut-off frequency of SIW, while achieves two transmission poles at the passband and two controllable transmission zero points. Furthermore, the novel loading scheme by loading different-sized DGS resonators on two sides of SIW is proposed for dual-band BPF designs. To validate the design and analysis, a 2.4/5.2 GHz filter prototype was designed. In good agreement with theoretical results, the measured results of the dual-band filter achieve insertion losses of 3.6 and 3.1 dB, and fractional bandwidths of 5.8% and 6.45% at 2.4 and 5.2 GHz, respectively. The filter size is only 408 mil × 420 mil.

To overcome limitations on bandwidth extension in conventional design techniques, a novel pole-converging technique with transformer feedback for intrastage bandwidth extension is proposed and analyzed in this paper. For verification, a three-stage cascode low-noise amplifier (LNA) based on the pole converging and negative drain-source transformer feedback is designed and implemented in a 65-nm CMOS technology. Consuming 27 mW dc power from a 1.8 V supply, the fabricated prototype exhibits peak power gain of 18.5 dB, minimum noise figure of 5.5 dB, 3-dB bandwidth of 30 GHz, and fractional bandwidth of 38.7%. The bandwidth of the three-stage cascode LNA is significantly extended without increasing power consumption and die size.

This paper presents the analysis and design of a novel broadband low-noise amplifier (LNA) with larger than seven-octave bandwidth. To achieve good impedance matching, flat gain, and low noise over larger than seven-octave bandwidth, the combination technique of shunt-resistive feedback, dual inductive-peaking techniques as well as a compact improved active load supporting broadband RF biasing from dc to 20 GHz, is proposed for LNA design. The gain and noise improvement principles of the proposed technique are also analyzed theoretically. Based on the theoretical study, a three-stage LNA with larger than seven-octave bandwidth, i.e. 0.1 to 20 GHz, is designed and verified using a 0.15-μm GaAs pHEMT technology. The LNA experimental results show a high gain of 28.6 dB, good noise figure of 3.1 to 5.8 dB, and output P ^-1 dB of 7.8 to 12.7 dBm over the broad frequency range of 0.1 to 20 GHz. The proposed LNA has a compact chip size of only 1.53 mm ² including testing input/output pads.

This paper presents the design of a compact 60-GHz phase shifter that provides a 5-bit digital phase control and 360° phase range for beam-forming systems. The phase shifter is designed using the proposed cross-coupled bridged T-type topology and switched-varactor reflective-type topology. The topologies are analyzed using a small-signal equivalent circuit model. Furthermore, the design equations are derived and investigated. To validate the theoretical analysis, 60-GHz 5-bit 360° phase shifters are designed in a commercial 65-nm CMOS technology. The fabricated 360° phase shifter features good performance of 32 phase states from 57 to 64 GHz with an rms phase error of 4.4°, a total insertion loss of 14.3 ± 2 dB, an rms gain error of 0.5 dB, P ₁ dB of better than 9.5 dBm, and the power consumption of almost zero. To the best of our knowledge, the designed 360° phase shifter with the size of 0.094 mm ² is the smallest 5-bit passive phase shifter at frequencies around 60 GHz.

This letter presents a wideband millimeter-wave low-noise amplifier (LNA) in a 65 nm CMOS technology. The amplifier adopts five-stage cascode topology with L-type input matching and T-type output matching. By distributing the peak gains of first four stages at two frequency points, the LNA achieves a flat gain response over a wide bandwidth. The measurement results show that the amplifier features a peak gain of 16.7 dB at 104 GHz, a minimum NF of 7.2 dB, and a 3 dB bandwidth of 21.5 GHz. The LNA consumes 48.6 mW and occupies a compact core area of 0.05 mm ² .

In this paper, the stress memorization technique (SMT) effects upon ultra-wideband RF switch performance are investigated for the first time. Low insertion loss (IL), high isolation, ultra-wideband (dc to 50 GHz) single-pole double-throw (SPDT), and single-pole four-throw (SP4T) switches designed with commercial 0.13- $\mu \text{m}$ high-resistivity (HR) trap-rich SOI technology with/without SMT are presented and investigated. 2.5 V nMOS transistor ( $L_{g} = 0.2~\mu \text{m}$ ) with low $R_{\mathrm{\scriptscriptstyle ON}} {^\ast} C_{\mathrm{\scriptscriptstyle OFF}}$ from GF 130RFSOI PDK is used. It is found that channel mobility of switch transistor is improved by SMT and thus switch performance can be further improved. Moreover, the impact of transistor channel length, which has dominant effects on both IL and isolation of the switches, under different gate bias on switch performance are also studied and verified experimentally. Low measured IL of less than 2.1 dB and good isolation of better than 27 dB from dc to 50 GHz are obtained for the SPDT switch. For SP4T switch, the measured IL of less than 2.6 dB and isolation of better than 27 dB are achieved from dc to 35 GHz. The active chip areas of designed SPDT and SP4T switches are compact with size of only $0.214 \times 0.19~\text {mm}^{2}$ and $0.36 \times 0.19~ \text {mm}^{2}$ , respectively.