Cryptography systems have become inseparable parts of almost every communication device. Among cryptography algorithms, public-key cryptography, and in particular elliptic curve cryptography (ECC), has become the most dominant protocol at this time. In ECC systems, polynomial multiplication is considered to be the most slow and area consuming operation. This article proposes a novel hardware architecture for efficient field-programmable gate array (FPGA) implementation of Finite-field multipliers for ECC. Proposed hardware was implemented on different FPGA devices for various operand sizes, and performance parameters were determined. Comparing to state-of-the-art works, the proposed method resulted in a lower combinational delay and area-delay product indicating the efficiency of design.

A physical unclonable function (PUF) is a promising lightweight circuit that provides security and authentication capability for electronic devices with low computational resources. Among various PUFs, the bistable ring PUF (BR-PUF) is considered one of the robust configurations. However, it has been shown that the challenge-response pairs (CRPs) from BR-PUF are vulnerable to statistical machine learning (ML) attacks, such as k-junta learning, support vector machine (SVM), and logistic regression (LR). In this article, we first show that the k-junta attack can break CRPs from the BR-PUF. Then, we present a hybrid chaotic-BR-PUF structure that obfuscates the BR-PUF response with the nonlinearized chaotic response. The proposed PUF structure has been implemented and experimentally evaluated on Xilinx Artix-7 FPGA, and the PUF measurements were captured. The proposed PUF was tested with a powerful statistical method developed using k-junta-based learning to confirm its strength against such attacks and evaluated using CRPs collected. The proposed PUF provides better resistance against ML attacks and reduces the learning accuracy to 50%-60% compared with previously proposed PUFs.

Finite field multiplication is a fundamental and frequently used operation in various cryptographic circuits and systems. Because of its high complexity, this operation generally determines the overall complexity and cost of these systems. Therefore, finite field multipliers and their hardware implementation have received considerable attention from researchers. This article proposes a methodology to design an efficient Galois field multiplier. First, space and time complexities for theoretical and field-programmable gate array (FPGA) implementations of M-term Karatsuba-like finite field multipliers were obtained. In addition, an algorithm was developed to obtain an efficient design based on a composite M-term Karatsuba-like multiplier. Furthermore, the proposed multipliers were verified and implemented on various FPGA devices, and implementation results were presented. Reported device utilization and latency indicated that the proposed multiplier is roughly 26% faster and 15% more efficient in the area–delay product compared to the standard Karatsuba multiplier. Moreover, comparison with state of the art also indicated that the proposed design is leading in terms of effectiveness and speed.

Mathematical modifications have been made to the Izhikevich Neuron Model to allow for a simple, low-area digital hardware implementation with low computational intensity. The implemented neuron circuit only requires one input parameter to replicate all of the cortical neuron behaviours described by Izhikevich. The low hardware requirements of this neuron implementation make large, highly parallel digital spiking neural networks of this neuron feasible. Additionally, the model requires fewer external parameter changes to exhibit diverse neuron behaviours. The alterations made to create this novel model are presented in detail with a performance comparison to the original Izhikevich Neuron. Subsequently a digital hardware realization is presented and its performance is characterized.

Directional overcurrent relays (DOCRs) depend on voltage and current measurements to initiate correct protection actions when faults occur. However, cyber-attacks can manipulate those measurements to make DOCRs output false tripping signals that may cause load shedding, power loss, and distribution lines isolation. Therefore, this paper employs Random Forest Decision (RFD), i.e., a machine learning algorithm, to detect and diminish false data injection attacks (FDIAs) and time synchronization attacks (TSAs) on inverse-time and time-current-voltage DOCRs. The employed RFD is trained to tackle grid faults and cyber-attack events as a classification problem. Thus, two classification types are considered: a binary classification that differentiates cyber-attacks from grid faults and a multi-class classification that identifies the attacked phase(s) and specifies the grid fault type. Furthermore, the training process for the binary and multi-class classification accounts for multiple noise levels that may affect the measured voltages and currents. The RFD is trained, validated, and tested on a Canadian benchmark distribution system. The results reveal the RFD’s ability to produce high-accuracy predictions to identify cyber-attacks and verify grid fault conditions without being affected by the system’s operating conditions and measurements’ noise.

Novel binary polynomial multipliers have been designed using M-term overlap-free Karatsuba multiplication (OFKM), where $M$ is 5–8. The proposed designs were realized in digital hardware and implemented on field-programmable gate array (FPGA) and the best value of $M$ was selected and presented for common National Institute of Standards and Technology (NIST) operand sizes from 64 to 571 bits. The implemented hardware designs use a hybrid approach that combines a given M-term overlap-free Karatsuba multipliers with two-term splitting to reduce the need for zero-padding in the final recurrent stages. Compared to the traditional M-term Karatsuba multipliers, the proposed overlap-free implementations offer reductions in delay and area-delay product (ADP). The proposed designs also compare favorably to previous implementations of binary polynomial multipliers. Their favorable characteristics make the proposed overlap-free Karatsuba polynomial multipliers viable options for use in cryptographic systems where speed is a significant consideration and hardware resource consumption must be limited.