Induction motors (IMs) are the backbone of industry, and play a vital role in daily life as well. However, induction motors face various faults during their operation, which may cause overheating, energy losses, and failure in the motors. Keeping in mind the severity of the issues associated with fault occurrence, this paper proposes a novel method of fault detection in induction motors by using “Machine Vision (MV)” along with “Infrared Thermography (IRT)”. It is worth mentioning that the timely prevention of faults in the IM ensures the motor’s safety from failures, and provides longer service life. In this work, a dataset of thermal images of an induction motor under different conditions (i.e., normal operation, overloaded, and fault) was developed using an infrared camera without disturbing the working condition of the motor. Then, the extracted thermal images were effectively used for the feature extraction and training by local octa pattern (LOP) and support-vector machine (SVM) classifiers, respectively. In order to enhance the quality of feature extraction from images, the LOP was implemented along with a genetic algorithm (GA). Finally, the proposed methodology was implemented and validated by detecting the faults introduced in an induction motor in real time. In addition to that, a comparative study of the suggested methodology with existing methods also verified the supremacy and effectiveness of the proposed method in comparison to the previous techniques.

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50nm, 90nm, and 120nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33GHz. Specifically, the 4-bit circuit of the proposed design in TSMCs 50nm technology consumes 25uW of power at 3.33GHz with 76ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature.